Today's most important topic in Backend vlsi signoff stage ERC (electrical rule check) ERC involves checking a design for all electrical connection. Checks such as well and substrate area for proper contact and spacing ,unconnected input or shorted output and one more Gates should not connect directly to supply (Must be connected through TIE high/low cells only) Floating gate errors ,if any gate is unconnected .This could lead to leakage issues. The well geometries need to be connected to power /ground and if PG Connection is not complete or if the pins are not defined ,the whole layout can report errors like"NWELL is not connected to VDD"
this is all about vlsi back end domains and description about synthesis,physical design and physical verification