Layout versus schematic(lvs): inputs are Spice Netlist(.lvs.v) and GDSii files( .gdsii ) and rule deck files. The Comparision two electrical circuits equivalent with respect to their "connectivity" and "total transistor count". And Comparision between (.gdsii) file and extrcted netlist (.lvs.v) file.Finally both are converted into a spice level . Lvs checks are: extract errors : · Shorts · Opens · Floating nets compare errors: · Pin errors · Parametric errors · Device mismatch · Net mismatch · Ports mismatch LVS process is dominated by two phases: extraction and circuit/layout comparison. An LVS tool is u...
this is all about vlsi back end domains and description about synthesis,physical design and physical verification