BackendVLSI

  Interview 1 What are the inputs of Physical design? What are the content in the .lib, .lef & .tlef files What are the challenges you faced in your design? If you say congestion, timing, latency then they will ask more question on these challenges. What is value of Tran, cap, latency and skew in your design? What are the OCV & AOCV? Why we go for POCV? What are the commands for multicycle path and generated clock? How you will confirm that netlist is proper? How to decide channel width between macros? Interview 2 What are ECO’s and what are the inputs need for ECO, why we need of it? What are metal ECO and Base ECO? What are the inputs of LVS? What is input and output delay? What is insertion delay? What is the clock period in your design and how many levels of clock has been built? Interview 3 What is DPT layers? How many DPT layers in your design? Why we are using DPT layers? What is the difference between FINFET and CMOS? Fin is gate or diffusion? How fin is connected t...