BackendVLSI

  In a   VLSI design , floorplan is the crucial stage in which chip area, size and shape of the chip can be determined. Floorplan is iterative process. When designer is done with the floorplan, the next step is to run placement and optimization, after completion of placement and optimization designer would analyse the congestion map, cell density and timing reports, before moving to next stage i.e. Clock Tree Synthesis. This article discusses about the various approaches to reduce congestion and timing violation by modifying floorplan at block level. The design complexity is increasing as the number of transistors on a chip is increasing. So, in the   VLSI design flow , Physical design plays a very important role. Floorplanning is the starting step in the physical design flow. The main concern of floorplanning is to find the appropriate location of the module on the layout surface on the basis of interconnectivity. While determining the locations, one important check invo...