SYNTHESIS CONCETPTS 1.what is synthesis 2.synthesis input files 3.goals of synthesis 4.synthesis process 5. .synthesis output files 6.Types of synthesis “ Synthesis transforms the RTL code of design modules into a gate-level netlist”. Important: This stage performs logic, area, power optimization, and scan insertion. Synthesis input files: 1. Timing library (.lib or .db) 2. Physical Library (lef, Milkyway) 3. SDC 4. RTL 5. DEF (For Physical aware Synthesis) 6. TLU+(Synopsys), Qrc(cadence) file 7. UPF Goal ...
this is all about vlsi back end domains and description about synthesis,physical design and physical verification