Netlist quality checks Below are certain checks that, should be fulfilled post-synthesis to ensure netlist qualifications before it is delivered for physical implementation. 1. No Clocks: In this check, we ensure that all the required clocks reach the sync points. Some major reasons for getting no clock violation in design are mentioned below: Clock definition missing: This is observed when clock creation is missing in the clock constraint file. RTL connectivity issue/Tie off: This type of no clock is observed when there is missing connectivity in between modules in the RTL or having direct tie-offs in the RTL. Impact: Ideally, all the registers in the design should be clocked. If no clock issue is left in the design, then it will report unconstraint endpoints and can cause optimization issues on such paths. Solution: To resolve the above-mentioned no clocks violation, we need to get the corrected RTL (from the designer) and clock constraints files with all the requir...
this is all about vlsi back end domains and description about synthesis,physical design and physical verification