BackendVLSI

 Outlined the tasks involved in the floorplanning phase of the chip design process. Here's a detailed breakdown of the steps. 1]Invoke the Tool 2]Open the Library and Block Created 3]Perform Sanity Checks 4]Create a Floorplan Define the core utilization, aspect ratio (width vs. height), chip shape, and space between the core and the die area. 5]Placing the I/O Ports 6]Placing Macros into the Core Area: 7]Set Keepout Margin and Fix the Macros 8]Add End Cap Cells 9]Add Tap Cells  10] Check Legality POWER PLANNING :  The power planning stage is a critical step in chip design, laying the groundwork for efficient and reliable power delivery throughout the chip. It's like building a robust power grid for your miniature city of transistors!  Goals of Power Planning: 1]Provide Efficient Power Supply to each component in the design 2]Power grid should meet the set IR drop targets. 3]Power grid should meet all EM targets. 4]Power grid should be optimal in terms of resource usage. Tasks I