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THINGS TO REMEMBER WHILE DOING PHYSICAL DESIGN

 Outlined the tasks involved in the floorplanning phase of the chip design process. Here's a detailed breakdown of the steps.

1]Invoke the Tool

2]Open the Library and Block Created

3]Perform Sanity Checks

4]Create a Floorplan

Define the core utilization, aspect ratio (width vs. height), chip shape, and space between the core and the die area.

5]Placing the I/O Ports

6]Placing Macros into the Core Area:

7]Set Keepout Margin and Fix the Macros

8]Add End Cap Cells

9]Add Tap Cells 

10] Check Legality

POWER PLANNING : 

The power planning stage is a critical step in chip design, laying the groundwork for efficient and reliable power delivery throughout the chip. It's like building a robust power grid for your miniature city of transistors! 


Goals of Power Planning:

1]Provide Efficient Power Supply to each component in the design

2]Power grid should meet the set IR drop targets.

3]Power grid should meet all EM targets.

4]Power grid should be optimal in terms of resource usage.


Tasks Involved In Power Planning

1]Invoke the tool

2]Open the Library and floorplan block

3]Perform Logical Connections

4]Set the attributes for Tie cells

5]Create Straps of VDD and VSS

6] Preroute Instances 

7]Create Rails for standard cell placement 

8]Create vias between Rails and Straps 

9]Verify the powerplan

PLACEMENT :

Placement is the process of placing  standard cells in the rows created at powerplan stage. Placement will be driven by different criteria like timing driven, congestion driven, power optimization etc. Timing and Routing depends on the quality of placement. 


Goals Of Placement

1]Achieve a database that is routable and timing clean.

2]Timing, Power and Area optimization.

3]Minimum Congestion

4]Minimum cell density and pin density.


Tasks Involved in Placement Stage

1]Invoke the tool

2]Open the library and powerplan block

3]Add I/O buffers 

4]Create Placement Blockages

5]Check_design - Pre Placement Stage

6]Perform Coarse Placement

7]Set parasitic parameters

8]Perform Placement optimization

9]Check legality

10]Check Global Route Congestion, Cell density and Pin density

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