Skip to main content

THINGS TO REMEMBER WHILE DOING PHYSICAL DESIGN

 Outlined the tasks involved in the floorplanning phase of the chip design process. Here's a detailed breakdown of the steps.

1]Invoke the Tool

2]Open the Library and Block Created

3]Perform Sanity Checks

4]Create a Floorplan

Define the core utilization, aspect ratio (width vs. height), chip shape, and space between the core and the die area.

5]Placing the I/O Ports

6]Placing Macros into the Core Area:

7]Set Keepout Margin and Fix the Macros

8]Add End Cap Cells

9]Add Tap Cells 

10] Check Legality

POWER PLANNING : 

The power planning stage is a critical step in chip design, laying the groundwork for efficient and reliable power delivery throughout the chip. It's like building a robust power grid for your miniature city of transistors! 


Goals of Power Planning:

1]Provide Efficient Power Supply to each component in the design

2]Power grid should meet the set IR drop targets.

3]Power grid should meet all EM targets.

4]Power grid should be optimal in terms of resource usage.


Tasks Involved In Power Planning

1]Invoke the tool

2]Open the Library and floorplan block

3]Perform Logical Connections

4]Set the attributes for Tie cells

5]Create Straps of VDD and VSS

6] Preroute Instances 

7]Create Rails for standard cell placement 

8]Create vias between Rails and Straps 

9]Verify the powerplan

PLACEMENT :

Placement is the process of placing  standard cells in the rows created at powerplan stage. Placement will be driven by different criteria like timing driven, congestion driven, power optimization etc. Timing and Routing depends on the quality of placement. 


Goals Of Placement

1]Achieve a database that is routable and timing clean.

2]Timing, Power and Area optimization.

3]Minimum Congestion

4]Minimum cell density and pin density.


Tasks Involved in Placement Stage

1]Invoke the tool

2]Open the library and powerplan block

3]Add I/O buffers 

4]Create Placement Blockages

5]Check_design - Pre Placement Stage

6]Perform Coarse Placement

7]Set parasitic parameters

8]Perform Placement optimization

9]Check legality

10]Check Global Route Congestion, Cell density and Pin density

Comments

Post a Comment

Popular posts from this blog

MOST IMPORTANT QUESTIONS FOR INTERVIEW

  Q 1: What are the goals of Synthesis Q 2: What are the Tech inputs in PNR Q 3: What are the Design inputs in PNR Q 4: What are the types of cells in PNR Q 5: What are the types of IO pads Q 6: What is the purpose of IO pads Q 7: What is the use of Bound pad Q 8: How tool differentiate the stdcell, IOpad and Macro Q 9: What is difference between soft and hard macro Q 10: How tool calculate the rectilinear blocks area Q 11: Can we rotated the Macro in 90 or 270 degrees Q 12: Assume you have three types of block 7, 9, 12 Metal layers in 28 nm Technology  which having more performance and why 13: Which inputs files having resistance and capacitance values Q 14: We have different RC corners im i right, why we have different RC corners Q 15: How multi cut via increase the performance and yeild. Q 16: In which stage normal flop converted into scan flop Q 17: what is difference between normal flop and scan flop Q 18: what is scan chain where we are ...
Post a Comment
Read more

Sanity Checks

  Netlist quality checks Below are certain checks that, should be fulfilled post-synthesis to ensure netlist qualifications before it is delivered for physical implementation. 1. No Clocks: In this check, we ensure that all the required clocks reach the sync points. Some major reasons for getting no clock violation in design are mentioned below: Clock definition missing: This is observed when clock creation is missing in the clock constraint file. RTL connectivity issue/Tie off: This type of no clock is observed when there is missing connectivity in between modules in the RTL or having direct tie-offs in the RTL. Impact:  Ideally, all the registers in the design should be clocked. If no clock issue is left in the design, then it will report unconstraint endpoints and can cause optimization issues on such paths. Solution:  To resolve the above-mentioned no clocks violation, we need to get the corrected RTL (from the designer) and clock constraints files with all the requir...
2 comments
Read more

QUESTION&ANSWERS

  Q 1: What are the goals of Synthesis ? There are Mainly three goals of synthesis without changing the functionality Reduce the area (chip cost reduce) Increase performance Reduce the power Q 2: What are the Tech dependent inputs in PNR There are three main tech depended inputs Physical libraries    -->format is .lef     --->given by vendors Technology file       -->format is .tf       --->given by fabrication peoples TLU+ file                   -->format is .TLUP-->given by fabrication people Q 3: What are the Design dependent inputs in PNR There are six main design depended inputs Logical libraries      --> format is .lib    --->given by Vendors Netlist          ...
Post a Comment
Read more