Q1: What are the goals of Synthesis Convert RTL → gate-level netlist Maintain functional correctness Meet timing (setup/hold) Optimize area and power Produce PnR-friendly netlist Output: Timing-clean, area/power optimized, tech-mapped netlist Q2: What are the Technology Inputs in PnR Technology-dependent files: LEF (Std cells, macros, IOs abstract) Tech LEF (Metal layers, vias, design rules) Liberty (.lib) (Timing, power) RC tech files (TLU+, ITF) Antenna rules DRC rules Q3: What are the Design Inputs in PnR Design-specific files: Netlist (.v) SDC (timing constraints) UPF/CPF (power intent) DEF (if floorplan exists) Scan DEF / DFT info Q4: What are the Types of Cells in PnR Standard cells Combinational Sequential (flops, latches) Macros Hard macros Soft macros IO cells Physical-only cells Fillers End caps Well taps Spare cells Q5: What are the Types of IO Pads Input pad Output pad Bidirectional pad Power pad (VDD) Ground pad (VSS) Corner pad Analog / special pads Q6: What is the ...
this is all about vlsi back end domains and description about synthesis,physical design and physical verification