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Questions and answers

 

Q1: What are the goals of Synthesis

Convert RTL → gate-level netlist

Maintain functional correctness

Meet timing (setup/hold)

Optimize area and power

Produce PnR-friendly netlist

Output: Timing-clean, area/power optimized, tech-mapped netlist

Q2: What are the Technology Inputs in PnR

Technology-dependent files:

LEF (Std cells, macros, IOs abstract)

Tech LEF (Metal layers, vias, design rules)

Liberty (.lib) (Timing, power)

RC tech files (TLU+, ITF)

Antenna rules

DRC rules

Q3: What are the Design Inputs in PnR

Design-specific files:

Netlist (.v)

SDC (timing constraints)

UPF/CPF (power intent)

DEF (if floorplan exists)

Scan DEF / DFT info

Q4: What are the Types of Cells in PnR

Standard cells

Combinational

Sequential (flops, latches)

Macros

Hard macros

Soft macros

IO cells

Physical-only cells

Fillers

End caps

Well taps

Spare cells

Q5: What are the Types of IO Pads

Input pad

Output pad

Bidirectional pad

Power pad (VDD)

Ground pad (VSS)

Corner pad

Analog / special pads

Q6: What is the Purpose of IO Pads

Interface between chip core and external world

Provide:

Signal buffering

ESD protection

Voltage level compatibility

Q7: What is the Use of Boundary Pad

Protects internal circuitry

Helps maintain:

Proper spacing

ESD safety

Acts as a buffer zone around die

Q8: How Tool Differentiates Std Cell, IO Pad, and Macro

Using LEF attributes:

CLASS CORE → Standard cell

CLASS BLOCK → Macro

CLASS PAD → IO pad

SIZE and FIXED property

Q9: Difference Between Soft and Hard Macro

Feature

Soft Macro

Hard Macro

Shape

Flexible

Fixed

Timing

Estimated

Accurate

Example

Synthesized block

SRAM, PLL

Placement

Tool can change

Fixed

Q10: How Tool Calculates Rectilinear Block Area

Area = Sum of all rectangles

Uses Manhattan geometry

Based on LEF macro definition

Q11: Can We Rotate Macro by 90° or 270°

YES, if allowed in LEF:

SYMMETRY X Y R90

NO, if rotation not defined

Memory macros often allow R0 / R180 only

Q12: 7, 9, 12 Metal Layers — Which Gives More Performance and Why

👉 12 metal layers

Reason:

More upper thick metals

Lower resistance

Less routing congestion

Better clock and power routing

Supports higher frequency designs

Q13: Which Input Files Have Resistance and Capacitance Values

TLU+ files

ITF files

.lib (cell internal RC)

Q14: Why Do We Have Different RC Corners

To model process variations

Different:

Temperature

Metal thickness

Width variation

Examples:

RCmin → Fast routing

RCmax → Worst delay

RCtyp

Q15: How Multi-Cut Via Improves Performance and Yield

Reduces via resistance

Improves current carrying capacity

Enhances electromigration reliability

Improves manufacturing yield

Q16: In Which Stage Normal Flop Converts to Scan Flop

👉 DFT / Scan insertion stage

After synthesis

Before PnR

Q17: Difference Between Normal Flop and Scan Flop

Normal Flop

Scan Flop

1 data input

2 inputs (D + Scan)

Functional mode

Test + functional

No scan enable

Has scan enable

Q18: What is Scan Chain and Where Is It Used

Chain of scan flops connected serially

Used during manufacturing testing

Improves observability and controllability

Q19: Formula for Core, Die, and Std Cell Utilization

Core Utilisation 

(Core Std Cell Area / Core Area) × 100

Die Utilization

(Core Area / Die Area) × 100

Std Cell Utilization

(Placed Std Cell Area / Placeable Core Area) × 100

Q20: Formula for Channel Spacing

Channel Width = Routing Demand / Routing Capacity

or practically:

Channel spacing = Track pitch × Number of tracks


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