LVS (Layout vs Schematic)

 Layout versus schematic(lvs):

inputs are Spice Netlist(.lvs.v) and GDSii files(.gdsii ) and rule deck files. 

The Comparision two electrical circuits equivalent with respect to their "connectivity" and "total transistor count". And Comparision between (.gdsii) file and extrcted netlist (.lvs.v) file.Finally both are converted into a spice level .

Lvs checks are:

extract errors :

·        Shorts

·        Opens

·        Floating nets

compare errors:

·        Pin errors

·        Parametric errors

·        Device mismatch

·        Net mismatch

·        Ports mismatch

LVS process is dominated by two phases: extraction and circuit/layout comparison. An LVS tool is used to extract a netlist from the layout, using device and net connectivity extraction techniques. Next, the tool compares the extracted layout netlist to the schematic netlist. Errors found during either extraction or comparison must be debugged.

During connectivity extraction, the assignment of multiple text names to the same polygon may leave the extraction process unable to clearly assign a net to that polygon. When this occurs, the extraction process selects one of the assigned names (with power having priority over signal) and identifies a “texted” short in that net. These texted shorts are typically one of the major debugging issues in the extraction phase. Debugging these shorts can be tricky, given that they can have many different causes and can cross design hierarchies. Large nets such as power and ground nets can often extend over an entire layout area, contain many polygons, and span multiple hierarchies, making a shorted power-ground net difficult and time-consuming to debug.

In the comparison phase, designers often encounter discrepancies such as cross-connection errors, bad instance-connection errors, open-circuit errors, short-circuit errors, and pin-swap errors. Debugging discrepancies revealed by comparing the layout and schematic has typically required designers to manually track and manage the corresponding elements while analyzing each discrepancy for its root cause. In very dense designs, this quickly becomes a time-consuming and frustrating task

Let’s use a simple pin-swap error to walk through the process. Pin-swap errors occur when two layout pins of an instance are cross-connected. Once the layout/schematic comparison is complete, designers can view a clear textual explanation of the pin swap discrepancy.

Main Realtime issues categories:

1.OPENS & SHORTS (Internal shorts with Macros)

2.Missing components

3.Missing global net connect