Synthesis Goals

                                                         SYNTHESIS 

         CONCETPTS

1.what is synthesis

2.synthesis input files

3.goals of synthesis

4.synthesis process

5. .synthesis output files

6.Types of synthesis

“ Synthesis transforms the RTL code of design modules into a gate-level netlist”. 

Important: This stage performs logic, area, power optimization, and scan insertion. 

Synthesis input files:

1.     Timing library (.lib or .db)

2.     Physical Library (lef, Milkyway)

3.     SDC

4.     RTL

5.     DEF (For Physical aware Synthesis)

6.     TLU+(Synopsys), Qrc(cadence) file

7.     UPF

Goal of Synthesis:

1.     Logic optimization with good QoR

2.     Scan insertion (DFT)

3.     Netlist generation

4.     Logical equivalence check should be preserved between the RTL and netlist

 

INPUTS :

1.     LIB: The timing library (.lib) contains information related to the timing, power, and area of standard cells. It also contains different PVT characterizations of cells.

2.     LEF: LEF represents the physical information of metal and via, standard cell, and macro.

3.     RTL: It’s a descriptive code written in HDL format.

4.     SDC: It represents the design constraint.

5.     DEF: DEF file contains the placement information of macro, pre-placed cells, IO ports, block size, and blockages. Mainly used for the Physical Aware synthesis.

6.     UPF: UPF file is required to describe the power intent of the design including the power domain, level shifter, isolation cell, and retention registers.

The synthesis process can be divided into three stages:

1.     Translation

2.     Optimization

3.     Mapping

Elaboration:

At this stage, it reads the RTL code, and this RTL code is converted into modules as per its logical hierarchy. Once it has all logical Boolean representation loaded, the tool maps logic with a technology-independent cell called the Gtech cell.

During elaboration, the tool checks whether the design is unique, if not, it stops the tool. Once the design becomes unique, the tool checks for unresolved references in the design. If it has linking issues, then an RTL correction is required, or you need to check if it is due to any missing libraries. After elaboration, it checks for timing loops in design. If you find any timing loop, you need to get RTL correction done by the designer.

Compile and optimization

After elaboration, in the compilation stage, the tool maps the Gtech cell with the actual cell (specific technology dependent) from the library. Actual cell mapping is dependent on the design constraints or user-specific constraints. Apart from this, the tool removes the registers with constant propagation/unloaded which are not required in the design. If these removed cells are required, then you need to provide feedback to the designer to get the correct RTL.

After elaboration and compilation, the tool performs optimizations based on user constraints to meet timing, area, and power requirements.

Outputs :

“A qualified netlist with scan insertion and good QoR in terms of timing, power, and area.”

Other outputs are updated DEF, UPF, and SDC.

1.     UPF: The output UPF is the updated version of the input UPF. At the synthesis stage, it performs logic optimization that introduces new power intents. So, we are generating UPF with this update after synthesis.

2.     DEF: While performing Physical Aware synthesis, we also generate the DEF file, which contains macro and standard cell placement information. This DEF is directly used in physical implementation that, avoids placement of the cell from scratch, hence, we can save run time.

3.     SDC: The output SDC is the updated version of the input SDC. At the synthesis stage, we use constraints provided by the designer. Additionally, we use certain local constraints to improve the overall QoR of design. Thus, the SDC with this update is generated after synthesis.

 

Types of Synthesis:

1. Logical Synthesis

Logical synthesis is a conventional synthesis, that processes the HDL (Verilog or VHDL) design and generates gate level netlist. During this process, the compiler optimizes the design based on predefined constraints.

2. Physical Aware Synthesis

Physical Aware synthesis requires additional floorplan DEF as an input. Floorplan DEF contains physical information like IO ports placements, macro placement information, blockages information and die area information. Additionally, we use RC co-efficient file as one of the inputs to compute a more accurate wire delay values compared to the WLM (Wire Load Model) method.

Advantages of Physical Aware synthesis:

1.     Better PPA (Power, Performance, Area).

2.     Better timing correlation with PNR.

3.     Better turnaround time (reduces the number of iterations).