BackendVLSI

  1. specification :   This is the first stage in the design process where we define the important parameters of the system that has to be designed into a specification . 2. Behavioural description :   T his is the stage where the design team and verification team come into the cycle where they generate RTL code using test benches. This is known as   behavioral simulation . 3 . RTL description :  RTL code is a set of code that checks whether the RTL implementation meets the design verification) is done in HDL, a lot of code coverage metrics are proposed for HDL. 4. functional verification :  Functional Verification is the process of verifying the functional characteristics of the design by generating different input stimuli and checking for correct behavior of the design implementation. 5. Logic synthesis: the process of converting get level netlist with their logical connectivity for simulated RTL code. In this synthesis, we can check not only functionality and also timing, area, pow

 

 For unsigned number computations, no need to add one more additional bit for computations or calculations. But, while doing signed numbers computations (-ve numbers), Then we need to add one more bit for signed representation. Then the total area, power, the cost will be more, due to increasing of area. To solve this problem, the alternate method is "complements". The complement is used for representing ' the negative decimal number in the binary form '. Different types of complement are possible of the binary number, but 1's and 2's complements are mostly used for binary numbers.  Generally, they are r's and (r-1)'s complement is possible, but                                                                                r---> should be is even number  Addition rules: subtraction rules: for subtractions : the complements are registers, especially for converting signed numbers. for signed numbers converting can be done by using either r's and (