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unlock surprise too see commands

                                  SynopsysTool Commands                                       How to add ndms in ref_libs Open block.tcl file Report_ref_libs information dump in a new tcl file Now go to icc2shell set_ref_libs -add missed ndm file---> from block.tcl file set_ref_libs -rebind link_block -force report_ref_libs save_block save_lib How to resolve upf error ? commit_upf save_block save_lib How to move ESD cell with origin coordinates ? move_objects [get_selection ] -to {7486.0965 3288.0000} How to select all the cells which have net name VDD_1V2_IO ?  change_selection [get_cells -of_objects [get_net VDD_1V2_IO]] Cmd for to check shorts  check_lvs -max_error 0 -checks short ----->for to check shorts How to add buffers add_buffer -lib_cell ec0cbf000an1n20x5 -new_cell_names 01122...
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QUESTION&ANSWERS

  Q 1: What are the goals of Synthesis ? There are Mainly three goals of synthesis without changing the functionality Reduce the area (chip cost reduce) Increase performance Reduce the power Q 2: What are the Tech dependent inputs in PNR There are three main tech depended inputs Physical libraries    -->format is .lef     --->given by vendors Technology file       -->format is .tf       --->given by fabrication peoples TLU+ file                   -->format is .TLUP-->given by fabrication people Q 3: What are the Design dependent inputs in PNR There are six main design depended inputs Logical libraries      --> format is .lib    --->given by Vendors Netlist          ...
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MOST IMPORTANT QUESTIONS FOR INTERVIEW

  Q 1: What are the goals of Synthesis Q 2: What are the Tech inputs in PNR Q 3: What are the Design inputs in PNR Q 4: What are the types of cells in PNR Q 5: What are the types of IO pads Q 6: What is the purpose of IO pads Q 7: What is the use of Bound pad Q 8: How tool differentiate the stdcell, IOpad and Macro Q 9: What is difference between soft and hard macro Q 10: How tool calculate the rectilinear blocks area Q 11: Can we rotated the Macro in 90 or 270 degrees Q 12: Assume you have three types of block 7, 9, 12 Metal layers in 28 nm Technology  which having more performance and why 13: Which inputs files having resistance and capacitance values Q 14: We have different RC corners im i right, why we have different RC corners Q 15: How multi cut via increase the performance and yeild. Q 16: In which stage normal flop converted into scan flop Q 17: what is difference between normal flop and scan flop Q 18: what is scan chain where we are ...
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