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Revision session

 10 Years Experienced Physical Design – Rapid Fire 100 Questions Interview Killer Revision Round (Senior / Lead Level) Use these for Qualcomm / Apple / NVIDIA / AMD / Intel / TSMC interviews. Answer in 1–3 lines, confident and practical. ⸻ Floorplan (1–15) 1. What is ideal utilization? No universal value; depends on macros, routing demand, node, timing target. Common start point high-60s to low-70s. 2. Why low utilization can also be bad? Wastes area, increases wirelength, hurts timing, higher die cost. 3. What is macro halo? Keepout around macro for routing/access/placement margin. 4. Channel spacing decided by? Pin density, expected traffic, metal stack, bus width. 5. Why macro orientation matters? Pin alignment and routing efficiency. 6. What makes floorplan good? Short critical paths, balanced whitespace, clean PG, low congestion risk. 7. Why place macros first? They dominate routing and topology. 8. Why edge macro placement common? Frees center for standard-cell routing. 9. Wh...
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ERC :ELECTRICAL RULE CHECK

 Today's most important topic in Backend vlsi signoff stage       ERC (electrical rule check) ERC involves checking a design for all electrical connection. Checks such as well and substrate area for proper contact and spacing ,unconnected input or shorted output and one more Gates should not connect directly to supply (Must be connected through TIE high/low cells only) Floating gate errors ,if any gate is unconnected .This could lead to leakage issues. The well geometries need to be connected to power /ground and if PG Connection is not complete or if the pins are not defined ,the whole layout can report errors like"NWELL is not connected to VDD"
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QUESTION&ANSWERS

  Q 1: What are the goals of Synthesis ? There are Mainly three goals of synthesis without changing the functionality Reduce the area (chip cost reduce) Increase performance Reduce the power Q 2: What are the Tech dependent inputs in PNR There are three main tech depended inputs Physical libraries    -->format is .lef     --->given by vendors Technology file       -->format is .tf       --->given by fabrication peoples TLU+ file                   -->format is .TLUP-->given by fabrication people Q 3: What are the Design dependent inputs in PNR There are six main design depended inputs Logical libraries      --> format is .lib    --->given by Vendors Netlist             ...
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