Skip to main content

ASIC FLOW Description

 1. specification: This is the first stage in the design process where we define the important parameters of the system that has to be designed into a specification.

2. Behavioural description: This is the stage where the design team and verification team come into the cycle where they generate RTL code using test benches. This is known as behavioral simulation.

3. RTL description: RTL code is a set of code that checks whether the RTL implementation meets the design verification) is done in HDL, a lot of code coverage metrics are proposed for HDL.

4. functional verification: Functional Verification is the process of verifying the functional characteristics of the design by generating different input stimuli and checking for correct behavior of the design implementation.

5. Logic synthesis: the process of converting get level netlist with their logical connectivity for simulated RTL code. In this synthesis, we can check not only functionality and also timing, area, power, and speed AS per designed specifications.

6. DFT: Design for testability in VLSI is a design technique that makes testing a chip possible. ... This DFT course is designed carefully based on the industry requirements, and it trains the electronics engineers extensively on VLSI design and Design for testability.

7. physical design: In RTL to GDS flow, Physical Design is an important stage. In physical design, synthesized netlist, design constraints, and standard cell library are taken as inputs and converted to a layout (GDS file) which should be as per the design rules provided by the foundry. 

8. sign off: In the signoff stage,we need to check

 1. Physical verification

 2. DRC (design rule checks )

 3. LVS ( Layout versus schematic )

 4. ERC (electrical rule check )

9. fabrication: Once the gate level simulations verify the functional correctness of the gate level design after the Placement and Routing phase, then the design is ready for manufacturing. 

10. packing and testing: The final GDS file (a binary database file format which is the default industry standard for data exchange of integrated circuit or IC layout artwork) is normally sent to a foundry that fabricates the silicon. Once fabricated, proper packaging is done and the chip is made ready for testing.

                                                                              

Labels:

Comments

Post a Comment

Popular posts from this blog

unlock surprise too see commands

                                  SynopsysTool Commands                                       How to add ndms in ref_libs Open block.tcl file Report_ref_libs information dump in a new tcl file Now go to icc2shell set_ref_libs -add missed ndm file---> from block.tcl file set_ref_libs -rebind link_block -force report_ref_libs save_block save_lib How to resolve upf error ? commit_upf save_block save_lib How to move ESD cell with origin coordinates ? move_objects [get_selection ] -to {7486.0965 3288.0000} How to select all the cells which have net name VDD_1V2_IO ?  change_selection [get_cells -of_objects [get_net VDD_1V2_IO]] Cmd for to check shorts  check_lvs -max_error 0 -checks short ----->for to check shorts How to add buffers add_buffer -lib_cell ec0cbf000an1n20x5 -new_cell_names 01122...
Post a Comment
Read more

MOST IMPORTANT QUESTIONS FOR INTERVIEW

  Q 1: What are the goals of Synthesis Q 2: What are the Tech inputs in PNR Q 3: What are the Design inputs in PNR Q 4: What are the types of cells in PNR Q 5: What are the types of IO pads Q 6: What is the purpose of IO pads Q 7: What is the use of Bound pad Q 8: How tool differentiate the stdcell, IOpad and Macro Q 9: What is difference between soft and hard macro Q 10: How tool calculate the rectilinear blocks area Q 11: Can we rotated the Macro in 90 or 270 degrees Q 12: Assume you have three types of block 7, 9, 12 Metal layers in 28 nm Technology  which having more performance and why 13: Which inputs files having resistance and capacitance values Q 14: We have different RC corners im i right, why we have different RC corners Q 15: How multi cut via increase the performance and yeild. Q 16: In which stage normal flop converted into scan flop Q 17: what is difference between normal flop and scan flop Q 18: what is scan chain where we are ...
Post a Comment
Read more

QUESTION&ANSWERS

  Q 1: What are the goals of Synthesis ? There are Mainly three goals of synthesis without changing the functionality Reduce the area (chip cost reduce) Increase performance Reduce the power Q 2: What are the Tech dependent inputs in PNR There are three main tech depended inputs Physical libraries    -->format is .lef     --->given by vendors Technology file       -->format is .tf       --->given by fabrication peoples TLU+ file                   -->format is .TLUP-->given by fabrication people Q 3: What are the Design dependent inputs in PNR There are six main design depended inputs Logical libraries      --> format is .lib    --->given by Vendors Netlist          ...
Post a Comment
Read more