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ASIC FLOW Description

 1. specification: This is the first stage in the design process where we define the important parameters of the system that has to be designed into a specification.

2. Behavioural description: This is the stage where the design team and verification team come into the cycle where they generate RTL code using test benches. This is known as behavioral simulation.

3. RTL description: RTL code is a set of code that checks whether the RTL implementation meets the design verification) is done in HDL, a lot of code coverage metrics are proposed for HDL.

4. functional verification: Functional Verification is the process of verifying the functional characteristics of the design by generating different input stimuli and checking for correct behavior of the design implementation.

5. Logic synthesis: the process of converting get level netlist with their logical connectivity for simulated RTL code. In this synthesis, we can check not only functionality and also timing, area, power, and speed AS per designed specifications.

6. DFT: Design for testability in VLSI is a design technique that makes testing a chip possible. ... This DFT course is designed carefully based on the industry requirements, and it trains the electronics engineers extensively on VLSI design and Design for testability.

7. physical design: In RTL to GDS flow, Physical Design is an important stage. In physical design, synthesized netlist, design constraints, and standard cell library are taken as inputs and converted to a layout (GDS file) which should be as per the design rules provided by the foundry. 

8. sign off: In the signoff stage,we need to check

 1. Physical verification

 2. DRC (design rule checks )

 3. LVS ( Layout versus schematic )

 4. ERC (electrical rule check )

9. fabrication: Once the gate level simulations verify the functional correctness of the gate level design after the Placement and Routing phase, then the design is ready for manufacturing. 

10. packing and testing: The final GDS file (a binary database file format which is the default industry standard for data exchange of integrated circuit or IC layout artwork) is normally sent to a foundry that fabricates the silicon. Once fabricated, proper packaging is done and the chip is made ready for testing.

                                                                              

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