BackendVLSI

 PERC is a reliability verification platform, providing robust, full chip, sign-off quality checks in an integrated environment. From your first schematic, through SoC assembly, to the final layout, we are able to provide a repeatable, efficient and effective reliability verification platform capable of verifying your most challenging reliability issues. the mix signal design, it is required to have different voltages to support each domain on the chip. However, designers have to make sure there is no signal line directly across from one voltage to another without any protection. Calibre PERC can help you to quickly find out if you have the right protections in your design. Electrostatic discharge (ESD) events causes severe damage to ICs. Several protection schemes have been proposed to mitigate this damage. Double diode ESD network is an example of a very common protection scheme for Input signals. Calibre PERC High Level Checks GUI enables the description of these protection circuits

Double patterning in VLSI:         Multi patterning also called double patterning ,double patterning is introduced 32nm and lowers layers 10nm,7nm etc.        Lithography pattern is a class of technologies for manufacturing IC's,developing for photolithography to enhance the feature of density and Optical microlithography (photolithography) is used for transferring the circuit patterns into silicon wafer.      We are use illuminator uv light to shine light through this mask producing an image of the pattern  through the lens system ,which eventually projected down into a photo resist coated silicon wafer using a protection system.      Double patterning is a technique that decomposes a single layout into two masks in order to increase pitch size and improve depth of focus.     Their resolution capabilities have fallen further and further behind the target minimum feature size per each advanced nodes.     their resolution capabilities have fallen further and further behind the targe

  Q 1: What are the goals of Synthesis ? There are Mainly three goals of synthesis without changing the functionality Reduce the area (chip cost reduce) Increase performance Reduce the power Q 2: What are the Tech dependent inputs in PNR There are three main tech depended inputs Physical libraries    -->format is .lef     --->given by vendors Technology file       -->format is .tf       --->given by fabrication peoples TLU+ file                   -->format is .TLUP-->given by fabrication people Q 3: What are the Design dependent inputs in PNR There are six main design depended inputs Logical libraries      --> format is .lib    --->given by Vendors Netlist                      --->format is .v       -->given by Synthesis People Synopsys Design Constraints  -->format is .SDC   -->given by Synthesis People MMMC         --> format is .tcl   --->given by Top level UPF --> format is .upf   --->given by Top level SCAN DEF