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PERC

 PERC is a reliability verification platform, providing robust, full chip, sign-off quality checks in an integrated environment. From your first schematic, through SoC assembly, to the final layout, we are able to provide a repeatable, efficient and effective reliability verification platform capable of verifying your most challenging reliability issues.

the mix signal design, it is required to have different voltages to support each domain on the chip. However, designers have to make sure there is no signal line directly across from one voltage to another without any protection. Calibre PERC can help you to quickly find out if you have the right protections in your design.

Electrostatic discharge (ESD) events causes severe damage to ICs. Several protection schemes have been proposed to mitigate this damage. Double diode ESD network is an example of a very common protection scheme for Input signals. Calibre PERC High Level Checks GUI enables the description of these protection circuits in the form of a Calibre rule-check with minimum effort. 

Electrical overstress (EOS) is responsible for the vast majority of device failures and product returns. The use of multiple voltages increases the risk of EOS, so IC designers need to increase their diligence to ensure that thin-oxide digital transistors do not have direct or indirect paths to high-voltage portions of the design.

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