Q 1: What are the goals of Synthesis
Q 2: What are the Tech inputs in PNR
Q 3: What are the Design inputs in PNR
Q 4: What are the types of
cells in PNR
Q 5: What are the types of IO
pads
Q 6: What is the purpose of
IO pads
Q 7: What is the use of Bound
pad
Q 8: How tool differentiate
the stdcell, IOpad and Macro
Q 9: What is difference
between soft and hard macro
Q 10: How tool calculate the
rectilinear blocks area
Q 11: Can we rotated the
Macro in 90 or 270 degrees
Q 12: Assume you have three
types of block 7, 9, 12 Metal layers in 28 nm Technology which having
more performance and why
13: Which inputs files having
resistance and capacitance values
Q 14: We have different RC
corners im i right, why we have different RC corners
Q 15: How multi cut via
increase the performance and yeild.
Q 16: In which stage normal
flop converted into scan flop
Q 17: what is difference
between normal flop and scan flop
Q 18: what is scan chain
where we are used it
Q 19: what is the formula for
core, die and std cell utilization
Q 20:what is the formula for
channel spacing
Q 21: How cell driving
strength increase
Q 22: How Fabrication peoples
created different types of Vt cells like HVT, +LVT and SVT etc.
Q 23: what is clock gating
why we are using clock gating what are the types of clock gating
Q 24:What is difference
between AND,OR and ICG based clock Gating
Q 25: What is pad limited and
Core limited Design how to overcome it
Q 26: What is difference
between IO PADS and IO PINS
Q 27: What is difference
between IO PIN and terminal
Q 28:What are the ways to
place IO pins in design
Q 29: What are the guidelines for pin placement
Q 30: Why we need MMMC file
Q 31: In which input file
having high fanout information
Q32: In which file noise
margin information content
Q 33: In which file cross
talk information contains
Q 34: what are the Macro
guidelines to place in floor plan
Q 35: what are the types of
blockage we used and why
Q 36:what is keep out margin
or halo
Q 37:what is difference
between keep out margin and blockage
Q 38:After loading Design
what are the sanity check we have to do and what you observe from that
Q 39:why we are using
Boundary or End cap cells. If we place this cells after placement what happened
Q40:Why we used Well Tap and
Tie cells if we are not use what happened
Q41:How you can estimate the
power for your design
Q42:What are the goals of
Power plan
Q43:what are the techniques
used to reduce IR drop
Q 44:what is formula for
dynamic and static power
Q 45:What is difference
between flip chip and wire bound design
Q 46: Why we are using Decap
cells and filler cells
Q47:What are the Floor
plan sanity checks
Q 48:can we do macro
placement after power plan
Q 49:can we do power plan
after routing
Q 50:What is Spare cells Why
we are using Spare cells
Q 51: In which
stage we are define spare cells
Q 52:What is the different
define Spare cells in floor plan and routing stage
Q 53:what are the ways to
place std cells in the core region
Q54:what are the five stages
of place_opt command and explain
Q 55:What is global routing
why we are doing global routing
Q 56: what are the goals of
placement
Q 57:what are the goals of floor plan
Q 58:What are the reason for
congestion how to fix the congestion
Q 59: How you can control the
std cell placement
Q 60:What are the types of
bounds
Q 61: If timing is bad in
your design after placement stage then what kind of technique you use to
overcome
Q 62:Can we do optimization
in placement stage without cell swapping upsizing and adding buffers
Q 63: Why we are checking
setup only in placement stage why we are not checking hold
Q 64: Why we are doing IO
buffering if we are not do IO buffering what happened
Q 65: What is pipeline
concept why we are using
Q 67: What are the sanity
check you did in placement stage and why
Q68:why we have to do scan
chain reorder in placement if not what happened
Q 69:You don't have any pin
& cell density and macro placement also good still your getting
congestion what would be the reason
Q 70:What are the types of
CTS
Q71:What is
difference between CPPR and CRPR
Q 72: Why we are building CTS
after placement only
Q 73: On which bases you will
say your skew is good
Q 74:Consider you have two
designs one have more skew and less latency one have less skew and more latency
which one you consider and why
Q75:My skew is Zero is good
or bad
76:what are the types of
skews and tool is work on which skew
Q 77:Consider I have two
design one have more latency one have less latency which one you choose and why
Q 78:On which reference CTS
will be build
Q 79:If I'm not define clock
can my CTS build or not
Q 80:What is inter clock balancing
Q 81:What is
useful skew how it is help for timing
Q 82:Flop having
setup and hold value I'm I right are those values constant or it can change🌐
Q 83:Are the flop
setup and hold values negative
Q 84:What is difference
between normal buffer and clock buffer
Q 85:For CTS building which
one you choose clock buffer or clock inverter
Q 86:What is CTS SPEC file
what it contain🌟
Q 87: If skew is bad how you
can overcome
Q 88: If latency is bad how
you can overcome
Q 89:How Skew effect on setup
and hold time
Q 90: Why we are using NDR in
CTS
Q 91:You have nine metal
layers in your design which metal layer you preferred for CTS and why
Q 92: what are the default
clock skew groups in design
Q 93:Explain clock_opt
command
Q 94:If clock is not
propagate what happened in CTS
Q 95:What are the sanity
check you did after CTS
Q 96:What is clock mesh were
we used it
Q 97: What is multi source
CTS why we used it
Q98: What is antenna effect
how to reduce
Q99:
What are the fixes for antenna effect
Q100: What is antenna ratio
where this information present
Q 101: what are the sanity
checks you did in routing stage
Q 102: What are the types of routing
Q 103: How many phases
routing will don
Q 104: What is detour how its
effect timing
Q 105:What is area recovery
and leakage recovery
Q 106:What are the types of
functional ECO and why we are doing it
Q 107: What are the Inputs
required for STA
Q108: What is the order of
timing fixing
Q 109: How to fix Max cap
Q 110:How to fix Max Tran
Q 111:How to fix Max fanout
Q 112:How to fix Setup
violation
Q 113:How to fix data to data
check violation
Q 114: How to fix Recovery
check violation
Q 115: How to fix Hold
violation
Q 116: How to fix Removal
violation
Q 117:How to fix Crosstalk
and noise
Q 118:How to fix clock gating
check
Q 119:How to fix antenna
violation
Q 120: what is positive and
negative cross talk
Q 121:What is LVS Check
Q 122:What is ERC check
Q 123:What is LEC check
Q 124:What is BEC check
Q 125:How to overcome shorts
and opens in your design
Q 126:what is sequential merging
Q 127:What is combinational
merging
Q 128:What is SVF file where
we used SVF file
Q 129:If LVS clean means we
can guarantee our design functionality
Q 130:How to fix IR drop
Q 131: How to fix EM
Q 132: How LEC work
Q 133:What are the ways to
reduce the Dynamic power consumption
Q 134:What is isolation cells
and what are the types of isolation cells
Q 135:Isolation cell
information present in which file
Q 136:What is power switch
why we used power switch what are the types of power switches
Q 137:What is Level
Shifter why we used it
Q 138: What is Enable Level
Shifter
Q 139: What Information
UPF/CPF file contains
Q 140:What is always ON
buffer where we used it
Q 141:What is the Purpose of
Double Patterning
Q 142:What is min Vt
violation how to overcome it.
Q 143:How we can analyze
clock tree and skew in placement stage only
Q 144:What we did in physical
verification stage
Q 145:How we get full GDS
Q 146:What is power gating
here we used it
Q 147:How to reduce static
power in Design
Q 148: What is difference
between DRC and DRV
Q 149:can you plz explain
timing ECO flow
Q 150:What is empty module
why we used it
Q 151:Why CMOS technology not
allowed Floating inputs and Multi driven inputs
Q152.How PERC works?
Q153.How to fix Signal integrity
Q154.What is ESD
Q155.How important coloring
in lower technology nodes
Q156.What are the Null shorts
Q157.Why Endcap cells placing
end of this block why not buffer or filler cells?
Q158.If Antenna error coming
higher layer of your design ,How you will fix Without placing diode and not go
for lower layers?
Q159.Why we are placing
placing Tapcells at Floorplan stage.
Q160.Why we are doing power
planning at Floorplan stage whynot after Placement?
Comments
Post a Comment