SynopsysTool Commands
How to add ndms in ref_libs
Open block.tcl file
Report_ref_libs information dump in a new tcl file
Now go to icc2shell
set_ref_libs -add missed ndm file---> from block.tcl file
set_ref_libs -rebind
link_block -force
report_ref_libs
save_block
save_lib
How to resolve upf error ?
commit_upf
save_block
save_lib
How to move ESD cell with origin coordinates ?
move_objects [get_selection ] -to {7486.0965 3288.0000}
How to select all the cells which have net name VDD_1V2_IO ?
change_selection [get_cells -of_objects [get_net VDD_1V2_IO]]
Cmd for to check shorts
check_lvs -max_error 0 -checks short----->for to check shorts
How to add buffers
add_buffer -lib_cell ec0cbf000an1n20x5 -new_cell_names 01122019_cell -new_net_names 01122019_net [get_pins lgcio_pch/giolgcpchtop/lgciopchdig/chaitanya_fix_3/clk]
For to check open nets for a specific net
check_lvs -checks open -nets {biss_bg_vref_out} -open_reporting detailed------>for to check opens of a specific net
How to load bumps
read_def -add_def_only_objects {cells nets ports} def file path
How to prepare Empty db
change_selection [get_cells *BUMP*]
remove_objects [get_selection ]
change_selection [get_shapes -of_objects -filter "layer_name==AP"]
change_selection [get_shapes -filter "layer_name==AP"]
change_selection [get_shapes -filter "layer_name==M11"]
change_selection [get_vias -filter "upper_layer_name==M11 || upper_layer_name==AP "]
remove_objects [get_selection ]
How to get def file?
Select whatever u need in tool then use below command
write_def -objects [get_selection] filename.def
How to load def?
First create empty db
Then use below command
read_def -add_def_only_objects {cells nets ports} def path
To create cell
create_cell inst_TMS_SWDIO */io_sndwire_fs_1v2_1v8_n1
move_objects [get_cell inst_1V8_SUP1V8_1 ] -to {4250.0000 0.0000}
To get cells
change_selection [get_cells -of_objects [get_nets VDD_DIG_BIS]]
sizeof_collection [get_cells]
To select all cells
lsort -u [get_attribute [get_selection ] object_class ]
Remove_cells [get_selection]
getting particular pins
get_pins par_opio/*xx*
connecting and disconnecting nets
Connect_net -net name pin name
Disconnect_net -net name pin name
cs [gp -of [gn vccvdd2_rpll_hv]]
get_nets -of_objects [gs]
How to remove terminals?
change_selection [get_terminals *]
remove_objects [get_selection]
How to take routes with tcl
Off terminal,ports,cells
First select nets
Give get selection
Then take that net names and paste in this cmnd on braces
1.change_selection [get_shapes -of_objects [get_nets netname]] then u will get that net nets shapes
2.change_selection [get_viass -of_objects [get_nets netname ]] -add
3. lsort -u [get_attribute [get_selection ] object_class ]
4.write_routes -objects [get_selection ] -output filename
To know width of the layer
ga [get_layer m9] min_width
For to remove cells from design
Remove_cellls [get_selection]
For to select that net shapes in specific Layer
change_selection [get_shapes -of_objects [get_net VDD_1V2_IO] -filter "layer_name==M10"]
For to know cell count
sizeof_collection [get_selection]
How to drop Vias in a perticular place by using commands.
By using bound option first create bound on that area
Next by using this command u can create vias for specific nets by selecting that bound
get_attribute [get_selection ] bbox
How to remove vias from a particular location
Here I am removing m10 vias
First draw bound on the area where u required.
Next use below commands
get_attribute [get_selection ] bbox
change_selection [get_vias -within {give bbox coordinates} -filter "upper_layer_name==M11 || upper_layer_name==M10"]
Get the count of Clock buffers?
report_device_group -detailed clock_network
llx lly urx ury all four coordinate of an instance
get_attribute [get_cells ctmTdsLR_1_31388] bbox
Get all the NDR used in the design
report_routing_rules
Get the routing status of a net
get_attribute [get_nets net_name ] physical status
Find the name of all the CTS clock nets
get_flat_nets -all -filter “net_type==clock”
Find the net name connected to a pin of an instance
get_nets -of_objects AES_core_keymem/key_mem_reg_9__90_/CP
Find the name of all the nets with a particular pattern in net name
get_nets <net_pattern*>
Get all the signal nets only (except clock, power and ground)
get_attribute [get_flat_nets -all -filter “net_type==signal”] name
Get the name of all the nets in the design
get_nets
Find the placement status of an instance
get_attribute [get_cells <cell_name>] physical_status
Get all nets having max fanout greater than specified number
report_net_fanout -threshold 50
Find the width and height of a cell
get_attribute [get_cells ctmTdsLR_1_31388] height
get_attribute [get_cells ctmTdsLR_1_31388] width
Get the temperature and delay corners of design
report_corners
Get the name of all the instance in your design which has fixed placement status
get_cells -filter “physical_status == fixed”
Find the name of all the don’t touch instance
report_dont_touch –all
Find the name of all sequential elements (registers/flip flops) in the design
get_attribute [ get_flat_cells -filter is_sequential ] name
Find the name of all the macro’s in your design
get_cells -filter “is_soft_macro == TRUE”
get_cells -filter “is_hard_macro == TRUE”
Find total numbers of well tap instances used in the design
sizeof_collection [get_cells *TAP*]
Find all the instances which have only one pins (like tie cells, antenna cells)
get_pins -of_objects [get_cells -filter “number_of_pins == 1” ]
Find the total number of physical cell instances used in the design
sizeof_collection [get_flat_cells -filter “is_physical_only == true”]
Get the clock skew and latency reports
report_clock_timing -type skew
report_clock_timing -type latency
report_clock_timing -type latency -nworst 20
Get all clock and scan clock pins
get_clock_tree_pins
Get all input and output ports
get_ports [all_inputs]
get_ports [all_outputs]
* Find the metal layers used in block level IO ports*
get_attribute [get_flat_cells *PAD*] layer_names
Get all the power domains available in the design
get_attribute [get_power_domains] name
Get the area and size of your block
get_attribute [current_block ] bbox
Get all the inverter and buffer cells available in the library
get_lib_cells -filter “is_buffer”
get_lib_cells -filter “is_inverter”
get all input ports exclude all clock ports
get_ports [remove_from_collection [all_inputs ] clk]
get all input ports excluding in specific pattern in the name
get_ports [remove_from_collection [all_inputs ] din* ]
*Get the information of a cell which is present in std. cell library but not in design.
get_lib_cells -of_objects [get_cells $cell_name ]
*Get the parameters of any particular routing layer (like Masks, Directions, pitch,
min-width, min-spacing etc )
report_design –floorplan *
Get all the routing layers name
get_attribute [get_layers ] name
Get all the layers name
get_attribute [get_layers *] name
Get all the pins of a selected Instance.
get_pins -of_objects [get_selection]
Get the cell name of a selected Instance.
get_selection [selected instance]
Find the top name of the design
current_design
Get the name of the selected object (instance, net, ports or any other objects).
get_attribute [get_selection ] name
Report the top worst failing 100 late timing paths with the endpoint and slack values
report_timing -path_type end -max_paths 100 -delay_type max
report_constraints –all_violators
Report the count of the unique lib cell types of all buffers/inverters in the data path
of a timing path.
get_lib_cells -of_objects <instance_name>
Find the CPPR value and CPPR branch point of a timing path. Report the
skew between the launch clock and capture clock of a timing path,
considering CPPR.
* Find the flops receiving no clocks*
check_timing
Find the number of logic depth (combinational) in a timing path.
/agnathavasi/procs/Synopsys/get_logic_depth.tcl
Source this proc and give timing path as arguments
*****************Get_logic_depths.tcl*******
proc get_logic_depth {my_path {exclude_unary “”} } {
set my_cells [get_cells -quiet -of \
[get_pins -quiet \
[get_attr -quiet \
[get_attr $my_path points] object] \
-f “pin_direction==in”] \
-f “is_combinational==true && defined (lib_cell)”]
if {$exclude_unary == “-exclude_unary”} {
set my_cells [filter_collection $my_cells “number_of_pins!=2”] }
return [sizeof_collection $my_cells]
}
define_proc_attributes get_logic_depth -info “Find Logic Depth of a Timing Path” \
-define_args {
{path “A single path collection” path list required} \
{-exclude_unary “Exclude Buffers/Inverters along the path” \
“\b” string optional}
}
#get_logic_depth [get_timing_paths -from AES_init_reg_reg -to AES_core_keymem/key_mem_reg_7__10_]
*************************************************************
Get drivers and receivers (loads) of a net.
get_cells -of_objects [get_pins -of_objects [get_nets so_out[42]]]
Query if a net is a clock net.
get_nets -hierarchical -filter “net_type == clk”
Check if a net is marked as dont_touch
get_attribute $net_name don’t_touch
Get the library name and base cell name of an instance.
get_lib_cells -of_objects [get_cells < cell_name >]
Get the maximum transition and maximum capacitance of a pin.
get_attribute [get_pins wn_PAD_3/C] min_capacitance
get_attribute [get_pins wn_PAD_3/C] max_capacitance
Find the clock period of a clock in a particular analysis view.
report_clocks -modes func
report_clocks -modes test
command to check unconnected pins & nets?
check_netlist
**********command to set analysis mode*******
Get the count of ULVT cells in the design (excluding physical only cells)
get_flat_cells -hierarchical -filter “ref_name =~ *ULVT*”
Get the edge number where a port is placed ?
How to add ndms in ref_libs
Open block.tcl file
Report_ref_libs information dump in a new tcl file
Now go to icc2shell
set_ref_libs -add missed ndm file---> from block.tcl file
set_ref_libs -rebind
link_block -force
report_ref_libs
save_block
save_lib
How to resolve upf error ?
commit_upf
save_block
save_lib
How to move ESD cell with origin coordinates ?
move_objects [get_selection ] -to {7486.0965 3288.0000}
How to select all the cells which have net name VDD_1V2_IO ?
change_selection [get_cells -of_objects [get_net VDD_1V2_IO]]
Cmd for to check shorts
check_lvs -max_error 0 -checks short----->for to check shorts
How to add buffers
add_buffer -lib_cell ec0cbf000an1n20x5 -new_cell_names 01122019_cell -new_net_names 01122019_net [get_pins lgcio_pch/giolgcpchtop/lgciopchdig/chaitanya_fix_3/clk]
For to check open nets for a specific net
check_lvs -checks open -nets {biss_bg_vref_out} -open_reporting detailed------>for to check opens of a specific net
How to load bumps
read_def -add_def_only_objects {cells nets ports} def file path
How to prepare Empty db
change_selection [get_cells *BUMP*]
remove_objects [get_selection ]
change_selection [get_shapes -of_objects -filter "layer_name==AP"]
change_selection [get_shapes -filter "layer_name==AP"]
change_selection [get_shapes -filter "layer_name==M11"]
change_selection [get_vias -filter "upper_layer_name==M11 || upper_layer_name==AP "]
remove_objects [get_selection ]
How to get def file?
Select whatever u need in tool then use below command
write_def -objects [get_selection] filename.def
How to load def?
First create empty db
Then use below command
read_def -add_def_only_objects {cells nets ports} def path
To create cell
create_cell inst_TMS_SWDIO */io_sndwire_fs_1v2_1v8_n1
move_objects [get_cell inst_1V8_SUP1V8_1 ] -to {4250.0000 0.0000}
To get cells
change_selection [get_cells -of_objects [get_nets VDD_DIG_BIS]]
sizeof_collection [get_cells]
To select all cells
lsort -u [get_attribute [get_selection ] object_class ]
Remove_cells [get_selection]
getting particular pins
get_pins par_opio/*xx*
connecting and disconnecting nets
Connect_net -net name pin name
Disconnect_net -net name pin name
cs [gp -of [gn vccvdd2_rpll_hv]]
get_nets -of_objects [gs]
How to remove terminals?
change_selection [get_terminals *]
remove_objects [get_selection]
How to take routes with tcl
Off terminal,ports,cells
First select nets
Give get selection
Then take that net names and paste in this cmnd on braces
1.change_selection [get_shapes -of_objects [get_nets netname]] then u will get that net nets shapes
2.change_selection [get_viass -of_objects [get_nets netname ]] -add
3. lsort -u [get_attribute [get_selection ] object_class ]
4.write_routes -objects [get_selection ] -output filename
To know width of the layer
ga [get_layer m9] min_width
For to remove cells from design
Remove_cellls [get_selection]
For to select that net shapes in specific Layer
change_selection [get_shapes -of_objects [get_net VDD_1V2_IO] -filter "layer_name==M10"]
For to know cell count
sizeof_collection [get_selection]
How to drop Vias in a perticular place by using commands.
By using bound option first create bound on that area
Next by using this command u can create vias for specific nets by selecting that bound
get_attribute [get_selection ] bbox
How to remove vias from a particular location
Here I am removing m10 vias
First draw bound on the area where u required.
Next use below commands
get_attribute [get_selection ] bbox
change_selection [get_vias -within {give bbox coordinates} -filter "upper_layer_name==M11 || upper_layer_name==M10"]
Get the count of Clock buffers?
report_device_group -detailed clock_network
llx lly urx ury all four coordinate of an instance
get_attribute [get_cells ctmTdsLR_1_31388] bbox
Get all the NDR used in the design
report_routing_rules
Get the routing status of a net
get_attribute [get_nets net_name ] physical status
Find the name of all the CTS clock nets
get_flat_nets -all -filter “net_type==clock”
Find the net name connected to a pin of an instance
get_nets -of_objects AES_core_keymem/key_mem_reg_9__90_/CP
Find the name of all the nets with a particular pattern in net name
get_nets <net_pattern*>
Get all the signal nets only (except clock, power and ground)
get_attribute [get_flat_nets -all -filter “net_type==signal”] name
Get the name of all the nets in the design
get_nets
Find the placement status of an instance
get_attribute [get_cells <cell_name>] physical_status
Get all nets having max fanout greater than specified number
report_net_fanout -threshold 50
Find the width and height of a cell
get_attribute [get_cells ctmTdsLR_1_31388] height
get_attribute [get_cells ctmTdsLR_1_31388] width
Get the temperature and delay corners of design
report_corners
Get the name of all the instance in your design which has fixed placement status
get_cells -filter “physical_status == fixed”
Find the name of all the don’t touch instance
report_dont_touch –all
Find the name of all sequential elements (registers/flip flops) in the design
get_attribute [ get_flat_cells -filter is_sequential ] name
Find the name of all the macro’s in your design
get_cells -filter “is_soft_macro == TRUE”
get_cells -filter “is_hard_macro == TRUE”
Find total numbers of well tap instances used in the design
sizeof_collection [get_cells *TAP*]
Find all the instances which have only one pins (like tie cells, antenna cells)
get_pins -of_objects [get_cells -filter “number_of_pins == 1” ]
Find the total number of physical cell instances used in the design
sizeof_collection [get_flat_cells -filter “is_physical_only == true”]
Get the clock skew and latency reports
report_clock_timing -type skew
report_clock_timing -type latency
report_clock_timing -type latency -nworst 20
Get all clock and scan clock pins
get_clock_tree_pins
Get all input and output ports
get_ports [all_inputs]
get_ports [all_outputs]
* Find the metal layers used in block level IO ports*
get_attribute [get_flat_cells *PAD*] layer_names
Get all the power domains available in the design
get_attribute [get_power_domains] name
Get the area and size of your block
get_attribute [current_block ] bbox
Get all the inverter and buffer cells available in the library
get_lib_cells -filter “is_buffer”
get_lib_cells -filter “is_inverter”
get all input ports exclude all clock ports
get_ports [remove_from_collection [all_inputs ] clk]
get all input ports excluding in specific pattern in the name
get_ports [remove_from_collection [all_inputs ] din* ]
*Get the information of a cell which is present in std. cell library but not in design.
get_lib_cells -of_objects [get_cells $cell_name ]
*Get the parameters of any particular routing layer (like Masks, Directions, pitch,
min-width, min-spacing etc )
report_design –floorplan *
Get all the routing layers name
get_attribute [get_layers ] name
Get all the layers name
get_attribute [get_layers *] name
Get all the pins of a selected Instance.
get_pins -of_objects [get_selection]
Get the cell name of a selected Instance.
get_selection [selected instance]
Find the top name of the design
current_design
Get the name of the selected object (instance, net, ports or any other objects).
get_attribute [get_selection ] name
Report the top worst failing 100 late timing paths with the endpoint and slack values
report_timing -path_type end -max_paths 100 -delay_type max
report_constraints –all_violators
Report the count of the unique lib cell types of all buffers/inverters in the data path
of a timing path.
get_lib_cells -of_objects <instance_name>
Find the CPPR value and CPPR branch point of a timing path. Report the
skew between the launch clock and capture clock of a timing path,
considering CPPR.
* Find the flops receiving no clocks*
check_timing
Find the number of logic depth (combinational) in a timing path.
/agnathavasi/procs/Synopsys/get_logic_depth.tcl
Source this proc and give timing path as arguments
*****************Get_logic_depths.tcl*******
proc get_logic_depth {my_path {exclude_unary “”} } {
set my_cells [get_cells -quiet -of \
[get_pins -quiet \
[get_attr -quiet \
[get_attr $my_path points] object] \
-f “pin_direction==in”] \
-f “is_combinational==true && defined (lib_cell)”]
if {$exclude_unary == “-exclude_unary”} {
set my_cells [filter_collection $my_cells “number_of_pins!=2”] }
return [sizeof_collection $my_cells]
}
define_proc_attributes get_logic_depth -info “Find Logic Depth of a Timing Path” \
-define_args {
{path “A single path collection” path list required} \
{-exclude_unary “Exclude Buffers/Inverters along the path” \
“\b” string optional}
}
#get_logic_depth [get_timing_paths -from AES_init_reg_reg -to AES_core_keymem/key_mem_reg_7__10_]
*************************************************************
Get drivers and receivers (loads) of a net.
get_cells -of_objects [get_pins -of_objects [get_nets so_out[42]]]
Query if a net is a clock net.
get_nets -hierarchical -filter “net_type == clk”
Check if a net is marked as dont_touch
get_attribute $net_name don’t_touch
Get the library name and base cell name of an instance.
get_lib_cells -of_objects [get_cells < cell_name >]
Get the maximum transition and maximum capacitance of a pin.
get_attribute [get_pins wn_PAD_3/C] min_capacitance
get_attribute [get_pins wn_PAD_3/C] max_capacitance
Find the clock period of a clock in a particular analysis view.
report_clocks -modes func
report_clocks -modes test
command to check unconnected pins & nets?
check_netlist
**********command to set analysis mode*******
command to get all signal nets only and whose fanout / pin count > 4 ?
get_pins -of_objects [get_fanets -filter “number_of_pins > 4” -filter “net_type ==signal”]
get_pins -of_objects [get_fanets -filter “number_of_pins > 4” -filter “net_type ==signal”]
Get the count of ULVT cells in the design (excluding physical only cells)
get_flat_cells -hierarchical -filter “ref_name =~ *ULVT*”
Get the edge number where a port is placed ?
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