Revision session

 10 Years Experienced Physical Design – Rapid Fire 100 Questions

Interview Killer Revision Round (Senior / Lead Level)

Use these for Qualcomm / Apple / NVIDIA / AMD / Intel / TSMC interviews.

Answer in 1–3 lines, confident and practical.

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Floorplan (1–15)

1. What is ideal utilization?

No universal value; depends on macros, routing demand, node, timing target. Common start point high-60s to low-70s.

2. Why low utilization can also be bad?

Wastes area, increases wirelength, hurts timing, higher die cost.

3. What is macro halo?

Keepout around macro for routing/access/placement margin.

4. Channel spacing decided by?

Pin density, expected traffic, metal stack, bus width.

5. Why macro orientation matters?

Pin alignment and routing efficiency.

6. What makes floorplan good?

Short critical paths, balanced whitespace, clean PG, low congestion risk.

7. Why place macros first?

They dominate routing and topology.

8. Why edge macro placement common?

Frees center for standard-cell routing.

9. What is feedthrough?

Signals crossing block through intermediate region.

10. Why avoid too many feedthroughs?

Congestion + latency.

11. What is aspect ratio impact?

Affects routing balance and wirelength.

12. Why square-ish blocks preferred?

Balanced horizontal/vertical routing.

13. What is pin planning goal?

Shortest external connectivity with manageable congestion.

14. Why blockages used?

Reserve routing/placement resources.

15. What is partial blockage?

Allows limited cell placement to reduce hotspots.

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Placement (16–30)

16. Main placement goal?

Legal, routable, timing-aware cell placement.

17. Why placement impacts timing?

Interconnect delay often dominates.

18. What causes congestion?

High density + connectivity demand.

19. Why cell spreading helps?

Reduces local route demand.

20. Why over-spreading hurts?

Longer wires.

21. What is legalization?

Move cells to legal rows/sites.

22. Why buffering inserted pre-route?

Improve slew/fanout/timing estimates.

23. Why high fanout bad?

Delay, transition, congestion.

24. What is scan chain reordering?

Reduce wirelength of scan connections.

25. Why timing worsens after legalization?

Cells move from optimal spots.

26. Why density screens used?

Control local placement density.

27. Why net delay > cell delay common?

Advanced nodes interconnect dominant.

28. What is useful clustering?

Physically grouping strongly connected logic.

29. Why many buffers indicate issue?

May signal poor topology or constraints.

30. What is placement QoR check?

WNS/TNS, congestion, DRVs, density.

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CTS (31–45)

31. Goal of CTS?

Controlled skew, acceptable latency, clean slew, low power.

32. What is skew?

Clock arrival difference between endpoints.

33. Positive skew effect?

Can help setup, hurt hold.

34. Negative skew effect?

Can help hold, hurt setup.

35. Why not zero skew?

Too costly/unnecessary.

36. What is insertion delay?

Source-to-flop clock latency.

37. Why high insertion delay bad?

Consumes timing budget, power.

38. Why hold explodes after CTS?

Balanced clocks expose short paths.

39. What is useful skew?

Intentional clock shift to improve timing.

40. Why clock buffers need care?

Power-heavy network.

41. Why shield clocks?

Reduce SI noise.

42. Why NDR for clock trunk?

Better RC / EM / SI.

43. Why leaf nets usually default route?

Too many leaves, area cost.

44. What is clock uncertainty?

Jitter + variation + modeling margin.

45. Why uncertainty dangerous?

Directly reduces available timing.

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Routing / SI (46–60)

46. What is global route?

Resource estimation path planning.

47. Detailed route?

Actual geometry routing.

48. Why route worsens timing?

Real RC and detours.

49. What is crosstalk?

Coupling effect between nearby nets.

50. Crosstalk hurts setup how?

Delay increase.

51. Crosstalk hurts hold how?

Can speed victim causing early arrival.

52. Why spacing helps SI?

Lower coupling capacitance.

53. Why wider wire helps?

Lower resistance.

54. Why wider wire can hurt too?

Higher area and ground cap.

55. Why via count matters?

Resistance/reliability.

56. What is antenna violation?

Charge accumulation risk during fabrication.

57. Fix antenna?

Diodes / layer jump / reroute.

58. Why upper metals used long nets?

Lower resistance, wider tracks.

59. Why route congestion dangerous?

Detours and DRC risk.

60. What is shielding?

Ground/power wire beside sensitive net.

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Timing (61–80)

61. Setup formula?

Required − arrival.

62. Hold formula?

Arrival(min) − required(min).

63. WNS?

Worst negative slack.

64. TNS?

Sum of negative slacks.

65. Which matters more?

WNS for peak issue, TNS for volume.

66. Why WNS improve but TNS worsen?

One path fixed, many degraded.

67. Why SS setup fail?

Slow devices.

68. Why FF hold fail?

Fast devices.

69. Net delay 70%. Fix?

Placement/routing first.

70. Cell delay 70%. Fix?

Sizing/Vt/logic first.

71. Why deep logic bad?

Accumulated delay.

72. 50-stage path always bad?

Depends on frequency and logic type.

73. Why LVT cells used?

Speed.

74. Why HVT cells used?

Leakage reduction.

75. Why not all LVT?

Power/leakage.

76. What is path group?

Categorized timing paths.

77. Why MCMM important?

One fix can fail another corner.

78. What is false path?

No functional timing requirement.

79. Multicycle path?

Allowed multiple cycles.

80. Danger of wrong exceptions?

Fake closure / silicon failure.

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Power / Reliability (81–90)

81. Dynamic power formula?

αCV²f

82. Leakage power depends on?

Vt, process, temperature.

83. Why clock power high?

High toggle + huge network.

84. What is IR drop?

Voltage loss in power network.

85. IR impact?

Slower cells, timing fail.

86. EM?

Metal wear from current density.

87. EM fix?

Wider wire, more vias, split current.

88. Why hotspots matter?

Thermal degrades reliability/timing.

89. Why decaps used?

Stabilize local supply.

90. Why power recovery after closure?

Remove unnecessary speedups.

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Ownership / Senior Level (91–100)

91. First step in any failure?

Classify root cause.

92. Random ECO or diagnosis?

Diagnosis first.

93. Tapeout under pressure strategy?

Prioritize highest-risk issues.

94. How to handle cross-team blame?

Single data review.

95. What is block ownership?

Driving closure end-to-end.

96. Best metric beyond WNS?

Trend + path family concentration.

97. What makes senior engineer?

Judgment and prioritization.

98. What makes lead engineer?

Multiply team effectiveness.

99. Biggest closure mistake?

Fixing symptoms not causes.

100. Why hire you?

I close difficult blocks systematically under pressure.

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Final Killer One-Liners

Use these in interviews:

* “Need root cause, not random ECO.”

* “Local congestion needs local fix.”

* “Interconnect dominates advanced nodes.”

* “One-corner clean means nothing without MCMM.”

* “Closure is prioritization under constraints.”