BackendVLSI

 10 Years Experienced Physical Design – Rapid Fire 100 Questions Interview Killer Revision Round (Senior / Lead Level) Use these for Qualcomm / Apple / NVIDIA / AMD / Intel / TSMC interviews. Answer in 1–3 lines, confident and practical. ⸻ Floorplan (1–15) 1. What is ideal utilization? No universal value; depends on macros, routing demand, node, timing target. Common start point high-60s to low-70s. 2. Why low utilization can also be bad? Wastes area, increases wirelength, hurts timing, higher die cost. 3. What is macro halo? Keepout around macro for routing/access/placement margin. 4. Channel spacing decided by? Pin density, expected traffic, metal stack, bus width. 5. Why macro orientation matters? Pin alignment and routing efficiency. 6. What makes floorplan good? Short critical paths, balanced whitespace, clean PG, low congestion risk. 7. Why place macros first? They dominate routing and topology. 8. Why edge macro placement common? Frees center for standard-cell routing. 9. Wh...