What are the goals of Synthesis ? There are Mainly three goals of synthesis without changing the functionality Reduce the area (chip cost reduce) Increase performance Reduce the Power What are the Tech dependent inputs in PNR There are three main tech depended inputs Physical libraries -->format is .lef --->given by vendors Technology file -->format is .tf --->given by fabrication peoples TLU+ file -->format is .TLUP-->given by fabrication people' Q 3: What are the Design dependent inputs in PNR There are six main design depended inputs Logical libraries --> format is .lib --->given by Vendors Netlist ...
this is all about vlsi back end domains and description about synthesis,physical design and physical verification