Skip to main content

digital design basics

 VLSI Technologies are now maturing with a current emphasis on submicron structures and sophisticated applications combining digital and analog circuits on a single chip.

here, we have 

1. digital :

digital means mainly,

switching circuits: because the voltage levels in a digital circuit are assumed to be switched from one value to another.

logic circuits: Each type of digital circuit obey a certain set of logic rules.

Digital circuits are one in which the voltage levels assume a finite number of the distance value.


2. Analog:

it was a continuously variable signal, analog circuits are those in which voltages and currents vary continuously through the given range. That can make infinite values within the specified range.

Started from :

1. Number system 

2. Grey coding

3. Complement's

4. Error detecting and decoding

5. Hamming code

6. Logic gates

7. Boolean algebra

8. K-maps 

9. Inverter

Number System:

It's a combination of different collections of numbers and it satisfies the same kind of requirements.

example: Decimal number systems

               Binary number systems



 1. Binary number system :

In a binary number (or base two) system, we use only two digits: 0 and 1






 2. decimal number system :

  A digital system can understand a positional number system only where there are a few symbols called digits and these symbols represent different values depending on the position they occupy in the number.


3. octal number system :

It is called the base 8 number system and It uses eight digits, 0,1,2,3,4,5,6,7.
.
example :

125708   = ((1 × 84) + (2 × 83) + (5 × 82) + (7 × 81) + (0 × 80))10

               = 549610

4. hexadecimal number system :

It is called the base 16 number system.It uses 10 digits and 6 letters, 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F.

19FDE16   = ((1 × 164) + (9 × 163) + (F × 162) + (D × 161) + (E × 160))10
                  = (65536 + 36864 + 3840 + 208 + 14)10    =10646210











Comments

Popular posts from this blog

Revision session

 10 Years Experienced Physical Design – Rapid Fire 100 Questions Interview Killer Revision Round (Senior / Lead Level) Use these for Qualcomm / Apple / NVIDIA / AMD / Intel / TSMC interviews. Answer in 1–3 lines, confident and practical. ⸻ Floorplan (1–15) 1. What is ideal utilization? No universal value; depends on macros, routing demand, node, timing target. Common start point high-60s to low-70s. 2. Why low utilization can also be bad? Wastes area, increases wirelength, hurts timing, higher die cost. 3. What is macro halo? Keepout around macro for routing/access/placement margin. 4. Channel spacing decided by? Pin density, expected traffic, metal stack, bus width. 5. Why macro orientation matters? Pin alignment and routing efficiency. 6. What makes floorplan good? Short critical paths, balanced whitespace, clean PG, low congestion risk. 7. Why place macros first? They dominate routing and topology. 8. Why edge macro placement common? Frees center for standard-cell routing. 9. Wh...

ERC :ELECTRICAL RULE CHECK

 Today's most important topic in Backend vlsi signoff stage       ERC (electrical rule check) ERC involves checking a design for all electrical connection. Checks such as well and substrate area for proper contact and spacing ,unconnected input or shorted output and one more Gates should not connect directly to supply (Must be connected through TIE high/low cells only) Floating gate errors ,if any gate is unconnected .This could lead to leakage issues. The well geometries need to be connected to power /ground and if PG Connection is not complete or if the pins are not defined ,the whole layout can report errors like"NWELL is not connected to VDD"

unlock surprise too see commands

                                  SynopsysTool Commands                                       How to add ndms in ref_libs Open block.tcl file Report_ref_libs information dump in a new tcl file Now go to icc2shell set_ref_libs -add missed ndm file---> from block.tcl file set_ref_libs -rebind link_block -force report_ref_libs save_block save_lib How to resolve upf error ? commit_upf save_block save_lib How to move ESD cell with origin coordinates ? move_objects [get_selection ] -to {7486.0965 3288.0000} How to select all the cells which have net name VDD_1V2_IO ?  change_selection [get_cells -of_objects [get_net VDD_1V2_IO]] Cmd for to check shorts  check_lvs -max_error 0 -checks short ----->for to check shorts How to add buffers add_buffer -lib_cell ec0cbf000an1n20x5 -new_cell_names 01122...