- What are lambda based design rules?
- What is nm in 10nm technology node?
- Do you know about under bum density?
- Any prior experience of PnR?
- How do you import design in PnR?
- Why ID layers have been given in lower nodes (10nm)?
- Why nwell continuity is required?
- Have you done scripting?
- Can you write an algorithm?
- What is drive strength?
- Why the industry is moving towards lower technology nodes like 7nm or 5nm?
- What are challenges seen in lower technology node?
- What are the difference between 45nm and 65nm routing rules? any new rule in the 45nm?
- Why foundry define DRM, routing rules?
- What is stack means? How many types of metal layers are in 65nm/45nm? Why metals are of different thickness?
- Why thin metal are in lower position and thick metals are at upper position in a defined Stack?
- What is the need of several types of metal layer in a design?
- What do you mean by RDL layer? Why it requires?
- How many types of routing? What is the sequence of that?
- Power is routed first or clock is routed first ? and why?
- what do you mean by notch rule? what is notch exactly (in terms of shape)?
- Why we code routing rules?
- What is stack VIA and why it requires?
- Why foundry define min spacing rules/min width rules?
- What do means by 65nm technology? Why it is saying 65nm?
- In terms of foundry what are the main difference in 65nm and 45nm technology? (means why technology is changing continuously? explanations from the foundry point of view.)
- What you think what are the challenges foundry face between two technology?
- what do u mean by crosstalk?
- How can you prevent this (crosstalk)?
- what do u mean by grid and non grid routing? which one is preferable and why?
- In magma tools , what is the concept behind sub grid?
- What are the different types of Grids?
- Why we use VIA array? Why not single large VIA in place of several via's?
- What do you mean by VIA overhang? Why it is needed?
- What do you mean by same grid spacing in VIAs?
- What is shielding? How can U shield a clock rail?
- The spacing between two single VIAs and spacing between via in VIA's array.. which one is smaller and why?
- How many types of spacing rules?
- How many types of width rules?
- What is fat wire? Why rules are define separately for this?
- How many layers are there in 130nm technology.
- What is min area rules?
- If the area of one metal layer is minimum from the min area rules then what should a designer do to prevent this?
- Routing rules are dependent on the types of metal used. Is it true or false and why?
- Why different types of metal layers (Al and Cu) are used in the design?
- What are the different types of Pitch?
- What do you mean by Pitch?
- What is antenna rules? Why it define? Explain from the point of view of foundry also.
- From where that accumulated charge come ?
- How this charge effect a gate? and why?
- How jumpers and diode prevent antenna violation?
- Which type of diode is used to prevent antenna violation and how it works?
- Where should be Jumper used?
- What are the different types of antenna violation rules?
- What is slotting rules?
- Why it define?
- How slots in the metal helps it?
- What is density rules?
- What is EM rules?
- Why they are define?
- How current density is dependent on temperature?
- How many types of rule are there in EM section?
- What is the significance of these rules from foundry point of view and from designer point of view?
- What are the difference between average current density and RMS current density? OR How many types of current density and what are the difference between them?
- Draw a diagram of CMOS. Explain different types of layers in it.
- What do you mean by diffusion layers?
- What is POD, NOD, Pwell, Nwell, N+,N++, P+, P++,Substrate, poly layer.
- What is Oxidation, Lithography?
- What is trench?
- What is masking?
- What is etching?
Q 1: What are the goals of Synthesis Q 2: What are the Tech inputs in PNR Q 3: What are the Design inputs in PNR Q 4: What are the types of cells in PNR Q 5: What are the types of IO pads Q 6: What is the purpose of IO pads Q 7: What is the use of Bound pad Q 8: How tool differentiate the stdcell, IOpad and Macro Q 9: What is difference between soft and hard macro Q 10: How tool calculate the rectilinear blocks area Q 11: Can we rotated the Macro in 90 or 270 degrees Q 12: Assume you have three types of block 7, 9, 12 Metal layers in 28 nm Technology which having more performance and why 13: Which inputs files having resistance and capacitance values Q 14: We have different RC corners im i right, why we have different RC corners Q 15: How multi cut via increase the performance and yeild. Q 16: In which stage normal flop converted into scan flop Q 17: what is difference between normal flop and scan flop Q 18: what is scan chain where we are ...
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