Skip to main content

Questions

  1. What are lambda based design rules?
  2. What is nm in 10nm technology node?
  3. Do you know about under bum density?
  4. Any prior experience of PnR?
  5. How do you import design in PnR?
  6. Why ID layers have been given in lower nodes (10nm)?
  7. Why nwell continuity is required?
  8. Have you done scripting?
  9. Can you write an algorithm?
  10. What is drive strength?
  11. Why the industry is moving towards lower technology nodes like 7nm or 5nm?
  12. What are challenges seen in lower technology node?
  13. What are the difference between 45nm and 65nm routing rules? any new rule in the 45nm?
  14. Why foundry define DRM, routing rules?
  15. What is stack means? How many types of metal layers are in 65nm/45nm? Why metals are of different thickness?
  16. Why thin metal are in lower position and thick metals are at upper position in a defined Stack?
  17. What is the need of several types of metal layer in a design?
  18. What do you mean by RDL layer? Why it requires?
  19. How many types of routing? What is the sequence of that?
  20. Power is routed first or clock is routed first ? and why?
  21. what do you mean by notch rule? what is notch exactly (in terms of shape)?
  22. Why we code routing rules?
  23. What is stack VIA and why it requires?
  24. Why foundry define min spacing rules/min width rules?
  25. What do means by 65nm technology? Why it is saying 65nm?
  26. In terms of foundry what are the main difference in 65nm and 45nm technology? (means why technology is changing continuously? explanations from the foundry point of view.)
  27. What you think what are the challenges foundry face between two technology?
  28. what do u mean by crosstalk?
  29. How can you prevent this (crosstalk)?
  30. what do u mean by grid and non grid routing? which one is preferable and why?
  31. In magma tools , what is the concept behind sub grid?
  32. What are the different types of Grids?
  33. Why we use VIA array? Why not single large VIA in place of several via's?
  34. What do you mean by VIA overhang? Why it is needed?
  35. What do you mean by same grid spacing in VIAs?
  36. What is shielding? How can U shield a clock rail?
  37. The spacing between two single VIAs and spacing between via in VIA's array.. which one is smaller and why?
  38. How many types of spacing rules?
  39. How many types of width rules?
  40. What is fat wire? Why rules are define separately for this?
  41. How many layers are there in 130nm technology.
  42. What is min area rules?
  43. If the area of one metal layer is minimum from the min area rules then what should a designer do to prevent this?
  44. Routing rules are dependent on the types of metal used. Is it true or false and why?
  45. Why different types of metal layers (Al and Cu) are used in the design?
  46. What are the different types of Pitch?
  47. What do you mean by Pitch?
  48. What is antenna rules? Why it define? Explain from the point of view of foundry also.
  49. From where that accumulated charge come ?
  50. How this charge effect a gate? and why?
  51. How jumpers and diode prevent antenna violation?
  52. Which type of diode is used to prevent antenna violation and how it works?
  53. Where should be Jumper used?
  54. What are the different types of antenna violation rules?
  55. What is slotting rules?
  56. Why it define?
  57. How slots in the metal helps it?
  58. What is density rules?
  59. What is EM rules?
  60. Why they are define?
  61. How current density is dependent on temperature?
  62. How many types of rule are there in EM section?
  63. What is the significance of these rules from foundry point of view and from designer point of view?
  64. What are the difference between average current density and RMS current density? OR How many types of current density and what are the difference between them?
  65. Draw a diagram of CMOS. Explain different types of layers in it.
  66. What do you mean by diffusion layers?
  67. What is POD, NOD, Pwell, Nwell, N+,N++, P+, P++,Substrate, poly layer.
  68. What is Oxidation, Lithography?
  69. What is trench?
  70. What is masking?
  71. What is etching?

Labels:

Comments

Post a Comment

Popular posts from this blog

Revision session

 10 Years Experienced Physical Design – Rapid Fire 100 Questions Interview Killer Revision Round (Senior / Lead Level) Use these for Qualcomm / Apple / NVIDIA / AMD / Intel / TSMC interviews. Answer in 1–3 lines, confident and practical. ⸻ Floorplan (1–15) 1. What is ideal utilization? No universal value; depends on macros, routing demand, node, timing target. Common start point high-60s to low-70s. 2. Why low utilization can also be bad? Wastes area, increases wirelength, hurts timing, higher die cost. 3. What is macro halo? Keepout around macro for routing/access/placement margin. 4. Channel spacing decided by? Pin density, expected traffic, metal stack, bus width. 5. Why macro orientation matters? Pin alignment and routing efficiency. 6. What makes floorplan good? Short critical paths, balanced whitespace, clean PG, low congestion risk. 7. Why place macros first? They dominate routing and topology. 8. Why edge macro placement common? Frees center for standard-cell routing. 9. Wh...
Post a Comment
Read more

ERC :ELECTRICAL RULE CHECK

 Today's most important topic in Backend vlsi signoff stage       ERC (electrical rule check) ERC involves checking a design for all electrical connection. Checks such as well and substrate area for proper contact and spacing ,unconnected input or shorted output and one more Gates should not connect directly to supply (Must be connected through TIE high/low cells only) Floating gate errors ,if any gate is unconnected .This could lead to leakage issues. The well geometries need to be connected to power /ground and if PG Connection is not complete or if the pins are not defined ,the whole layout can report errors like"NWELL is not connected to VDD"
Post a Comment
Read more

QUESTION&ANSWERS

  Q 1: What are the goals of Synthesis ? There are Mainly three goals of synthesis without changing the functionality Reduce the area (chip cost reduce) Increase performance Reduce the power Q 2: What are the Tech dependent inputs in PNR There are three main tech depended inputs Physical libraries    -->format is .lef     --->given by vendors Technology file       -->format is .tf       --->given by fabrication peoples TLU+ file                   -->format is .TLUP-->given by fabrication people Q 3: What are the Design dependent inputs in PNR There are six main design depended inputs Logical libraries      --> format is .lib    --->given by Vendors Netlist             ...
Post a Comment
Read more