BackendVLSI

  1. Practical flow of the design? 2. How analog macro is placed? 3. Explain the power plan structure in your design? 4. What is the routing blockage for analog macro? 5. What are the checks after the floorplan? 6. What are the steps in the placement stage? 7. What is the block size, utilization, target skew, WNS of your design? 8. What are the corners in your design? 9. What are the corners considered in the placement stage? why? 10. What are the corners considered in the CTS stage? why? 11. What are the causes for congestion. And how to fix it? 12. What could be the reason for congestion, if there is neither cell density nor pin density and also, there is no much communication between nearest macro and std cells as well? 13. How to fix setup and hold issues? 14. Give the order of priority among various setup fixing methods? And reasons for them? 15. How tran Violation will affect the setup? 16. In case, there are 10000 setup violations in the placement stage, what could be the issue?

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                                                          SYNTHESIS           CONCETPTS 1.what is synthesis 2.synthesis input files 3.goals of synthesis 4.synthesis process 5. .synthesis output files 6.Types of synthesis “ Synthesis transforms the RTL code of design modules into a gate-level netlist”.  Important: This stage performs logic, area, power optimization, and scan insertion.  Synthesis input files: 1.      Timing library (.lib or .db) 2.      Physical Library (lef, Milkyway) 3.      SDC 4.      RTL 5.      DEF (For Physical aware Synthesis) 6.      TLU+(Synopsys), Qrc(cadence) file 7.      UPF Goal of Synthesis: 1.      Logic optimization with good QoR 2.      Scan insertion (DFT) 3.      Netlist generation 4.      Logical equivalence check should be preserved between the RTL and netlist   INPUTS : 1.      LIB:  The timing library (.lib) contains information related to the timing, power, and area of standard cells. It also contains different PVT characterizations of cells. 2.