Skip to main content

question -1

 1. Practical flow of the design?

2. How analog macro is placed?

3. Explain the power plan structure in your design?

4. What is the routing blockage for analog macro?

5. What are the checks after the floorplan?

6. What are the steps in the placement stage?

7. What is the block size, utilization, target skew, WNS of your design?

8. What are the corners in your design?

9. What are the corners considered in the placement stage? why?

10. What are the corners considered in the CTS stage? why?

11. What are the causes for congestion. And how to fix it?

12. What could be the reason for congestion, if there is neither cell density nor pin density and

also, there is no much communication between nearest macro and std cells as well?

13. How to fix setup and hold issues?

14. Give the order of priority among various setup fixing methods? And reasons for them?

15. How tran Violation will affect the setup?

16. In case, there are 10000 setup violations in the placement stage, what could be the issue?

17. What kind of constraint will lead to so many setup violations in the placement stage?

18. How to analyze timing reports. And how the approach will be for fixing slack?

19. If there are many shorts at one place in the routing stage, what could be the possible reason?

20. What are the checks after CTS?

21. Why we check hold after CTS?

22. What are the checks after routing?

23. What are the different kinds of DRC checks?

24. In case there are many shorts, opens, setup, hold violations...what you will address first?

25. What are tap cells? How much distance given in your design and why?

26. What is the use of tap cell?

27. If we don’t use tap cells, what error we will get?

28. What are low power techniques?

29. Explain isolation cell, retentions cell, power switches, and level shifters.

30. How to fix static and dynamic IR issues.

31. Assume there are 6 timing corners, if the hold is not able to fix in one corner, how to fix it without

affecting the other corners. What is the better approach to fix it without affecting others?

32. Write few commands from ICC2, INNOVUS?

  1. What is placement and what are goals of placement?
  2. What are the things to be checked before going to placement stage?
  3. What are the inputs and outputs for placement stages?
  4. After floorplan DEF is generated as input of placement stage what it contains?
  5. What are the challenges faced in placement stages?
  6. What are reasons of congestion in the design?
  7. What are the different methods of tackling congestion? Where do you find major congestion in your design?
  8. How do you tackle congestion in the core area? You have a region with pin density high and the router is not able to route to these pins. How to resolve this issue?
  9. How to tackle cell density issue?
  10. At what stage do you start looking at your timing reports in the PD flow?
  11. How will you check your timing report? What are the things you will look into it in case of timing violation?
  12. What are the types of placement?
  13. During placement stage how tool will know that your design is getting congestion without doing the actual route?
  14. What types of routing is carried out by the tool in placement stage global routing or virtual routing?
  15. What happens in global routing?
  16. What are the switches in place_opt command and how they are useful?
  17. What happens during congestion driven techniques? What are the care should be taken using congestion driven option?
  18. What are the types of congestion? And solution to resolve congestion?
  19. How to modify physical constraints to reduce the congestion?
  20. What happens if you over do keepout margin?
  21. How many blockages are there in your design, how will you define the blockages and keepout margins (halo)?
  22. What do you mean by logic optimization techniques and give some examples of logic optimization?
  23. How do you used blockages techniques to effectively reduce congestion?
  24. What is magnet placement?
  25. What is multibit banking and why we use it and what are the advantages and disadvantages of that?
  26. What is fan-out? What is HFN synthesis why we do it in placement stage? Can we consider clock in HFN during placement stages?
  27. How global route will handle congested paths?
  28. What do you means by scan chain reordering why we used it?
  29. How to qualify the placement stage?
  30. What are the challenge you will see in lower technology?
  31. What are the inputs and outputs from the power analysis?
  32. What are the checks after power planning is completed?
  33. What are the power dissipation components? How to reduce them
  34. Why float outputs are ignored but not float gates?
  35. How do you calculate the core ring width?
  36. What is IR drop? And how will you decrease this?
  37. What are general power margins?
  38. During power analysis, if you are facing IR drop problem, then how did you avoid that.
  39. What are the effects of IR drop?
  40. How IR drop affects setup and hold timing?
  41. Why high metal layers are preferred for VDD and VSS
  42. How to find number of power pads and IO power pads. How the width of metal and numbers of straps calculated for power and ground.
  43. What is power gating?
  44. CMOS power consumption details? Different types
  45. How you make sure that power structure is good?
  46. What is short circuit current and how will you overcome this problem?
  47. What is difference between static IR drop and dynamic IR drop?
  48. On what all parameter static IR drop and dynamic IR drop depends on?
  49. What is the purpose of static IR drop?
  50. How to reduce power/ground bounce?
  51. How you will fix EM violations. What are the step to minimize Electromigration?
  52. What is clock gating?
  53. Why is power planning done and how? Which metal should we use for power and ground rings & straps and why?
  54. What is the difference between level shifter and isolations cells?
  55. What is isolations cells and its types?
  56. How to find total power chip, what are the problems you can faced with respect to timing?
  57. How the numbers of power straps calculate.
  58. How did you do floorplanning?
  59. How to calculate core ring width, macro ring width and straps or trunk width?
  60. How do you reduce power dissipation using high VT and Low VT on your design?
  61. What are the various statistics available in IR drop reports?
  62. What is the importance of IR DROP analysis?
  63. What are low power techniques?
  64. What is the difference between footer switch and header switch in power gating?
  65. What is EM self-heating?
  66. How the cell modeled while power analysis?
  67. How core ring length matters while deciding the core ring width?
  68. After adding power straps if you have hot spot what to do?
  69. How to calculate core ring and straps width?
  70. How do you reduce standby (leakage) power?
  71. How to do power planning for multi voltage design?
  72. What is the tradeoff between dynamic power (current) and leakage power (current)?
  73. What are the power dissipation component? How to reduce them?
  74. What are the different reason for high voltage drop in the design?
  75. What is the need of UPF and what are the contents in UPF? Is always on cell present in UPF or not?
  76. If you have analog and digital (RAM) macros in your design how to do floorplanning?
  77. How many power domains are there in your project and how are they interlinked with each other?
  78. What is the issue if we see the design having current more than its defined capacity?
  79. How to reduce glitches power violations in the design?
  80. Explain power routing structure in your design?

Labels:

Comments

Post a Comment

Popular posts from this blog

MOST IMPORTANT QUESTIONS FOR INTERVIEW

  Q 1: What are the goals of Synthesis Q 2: What are the Tech inputs in PNR Q 3: What are the Design inputs in PNR Q 4: What are the types of cells in PNR Q 5: What are the types of IO pads Q 6: What is the purpose of IO pads Q 7: What is the use of Bound pad Q 8: How tool differentiate the stdcell, IOpad and Macro Q 9: What is difference between soft and hard macro Q 10: How tool calculate the rectilinear blocks area Q 11: Can we rotated the Macro in 90 or 270 degrees Q 12: Assume you have three types of block 7, 9, 12 Metal layers in 28 nm Technology  which having more performance and why 13: Which inputs files having resistance and capacitance values Q 14: We have different RC corners im i right, why we have different RC corners Q 15: How multi cut via increase the performance and yeild. Q 16: In which stage normal flop converted into scan flop Q 17: what is difference between normal flop and scan flop Q 18: what is scan chain where we are used it
Post a Comment
Read more

Double patterning ?

Double patterning in VLSI:         Multi patterning also called double patterning ,double patterning is introduced 32nm and lowers layers 10nm,7nm etc.        Lithography pattern is a class of technologies for manufacturing IC's,developing for photolithography to enhance the feature of density and Optical microlithography (photolithography) is used for transferring the circuit patterns into silicon wafer.      We are use illuminator uv light to shine light through this mask producing an image of the pattern  through the lens system ,which eventually projected down into a photo resist coated silicon wafer using a protection system.      Double patterning is a technique that decomposes a single layout into two masks in order to increase pitch size and improve depth of focus.     Their resolution capabilities have fallen further and further behind the target minimum feature size per each advanced nodes.     their resolution capabilities have fallen further and further behind the targe
Post a Comment
Read more

Synthesis Goals

                                                          SYNTHESIS           CONCETPTS 1.what is synthesis 2.synthesis input files 3.goals of synthesis 4.synthesis process 5. .synthesis output files 6.Types of synthesis “ Synthesis transforms the RTL code of design modules into a gate-level netlist”.  Important: This stage performs logic, area, power optimization, and scan insertion.  Synthesis input files: 1.      Timing library (.lib or .db) 2.      Physical Library (lef, Milkyway) 3.      SDC 4.      RTL 5.      DEF (For Physical aware Synthesis) 6.      TLU+(Synopsys), Qrc(cadence) file 7.      UPF Goal of Synthesis: 1.      Logic optimization with good QoR 2.      Scan insertion (DFT) 3.      Netlist generation 4.      Logical equivalence check should be preserved between the RTL and netlist   INPUTS : 1.      LIB:  The timing library (.lib) contains information related to the timing, power, and area of standard cells. It also contains different PVT characterizations of cells. 2.
Post a Comment
Read more