vlsi companies in india

1.qualcomm

2.nividia

3.samsung

4.intel

5.google

6.AMD

7.MediaTek

8.Apple

9.NXP

10.Broadcom

11.western digital

12.synopsys

13.capgemini

14.Cadence

15.Micron Technology

16.xilinx

17.marvel technology

18.silicon labs

19.einfochips

20.moschip

21.tech mahindra

22.synapse

23.ust global

24.mirafra

25.HCL

26.ASM Technologies

27.adept chip services

28.cientra

29.insemi

30.altran

31.cypress semiconductors

32.wipro

33.truechip

34.smartsoc

35.digicomm

36.ACL Digital

37.leadsoc

38.tessolve

39.soctronics

40.IBM

41.sibridge technologies

42.excelmax

43.pozibility technology

44.bitsilica

45.niksperri technologies

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MOST IMPORTANT QUESTIONS FOR INTERVIEW

Q 1: What are the goals of Synthesis Q 2: What are the Tech inputs in PNR Q 3: What are the Design inputs in PNR Q 4: What are the types of cells in PNR Q 5: What are the types of IO pads Q 6: What is the purpose of IO pads Q 7: What is the use of Bound pad Q 8: How tool differentiate the stdcell, IOpad and Macro Q 9: What is difference between soft and hard macro Q 10: How tool calculate the rectilinear blocks area Q 11: Can we rotated the Macro in 90 or 270 degrees Q 12: Assume you have three types of block 7, 9, 12 Metal layers in 28 nm Technology which having more performance and why 13: Which inputs files having resistance and capacitance values Q 14: We have different RC corners im i right, why we have different RC corners Q 15: How multi cut via increase the performance and yeild. Q 16: In which stage normal flop converted into scan flop Q 17: what is difference between normal flop and scan flop Q 18: what is scan chain where we are ...

Sanity Checks

Netlist quality checks Below are certain checks that, should be fulfilled post-synthesis to ensure netlist qualifications before it is delivered for physical implementation. 1. No Clocks: In this check, we ensure that all the required clocks reach the sync points. Some major reasons for getting no clock violation in design are mentioned below: Clock definition missing: This is observed when clock creation is missing in the clock constraint file. RTL connectivity issue/Tie off: This type of no clock is observed when there is missing connectivity in between modules in the RTL or having direct tie-offs in the RTL. Impact: Ideally, all the registers in the design should be clocked. If no clock issue is left in the design, then it will report unconstraint endpoints and can cause optimization issues on such paths. Solution: To resolve the above-mentioned no clocks violation, we need to get the corrected RTL (from the designer) and clock constraints files with all the requir...

QUESTION&ANSWERS

Q 1: What are the goals of Synthesis ? There are Mainly three goals of synthesis without changing the functionality Reduce the area (chip cost reduce) Increase performance Reduce the power Q 2: What are the Tech dependent inputs in PNR There are three main tech depended inputs Physical libraries -->format is .lef --->given by vendors Technology file -->format is .tf --->given by fabrication peoples TLU+ file -->format is .TLUP-->given by fabrication people Q 3: What are the Design dependent inputs in PNR There are six main design depended inputs Logical libraries --> format is .lib --->given by Vendors Netlist ...

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