BackendVLSI

  Minimizing power consumption is a major factor that contributes to the modern-day development of IC designs, especially in the consumer electronics segment. The heating of the devices, the time it takes to turn on/off the features of handheld devices, battery life, etc are still under reforms. Hence it becomes important that best practices of chip design are adopted to aid the power consumption in SoCs (System on Chip) The performance of the Silicon is greatly influenced by power management for SoCs and RTL designs. To attain power statistics, industries utilize power-aware designs. This blog's focus is on multi-Voltage design terminology that can be used in HDL coding to determine silicon's power performance. These aid in comprehending the design parameters when putting into practice power-conscious designs. Multiple Voltage Design (Multi Voltage Power Domain) Method Power supply has a direct relationship with dynamic power which consists of switching & short-circuit pow

  What are the types of bounds ? There are two types of bounds move bound and group bound & Move bounds means with definite coordinate if we created bound that's we called move bounds this are three types Soft move bound: In optimization some cells are go out from the bound to meet timing QOR other logic cell comes and site in that bound Hard move bound: The cells should not move out and other cells are allowed in that bound Exclusive move bound : The cells not move out and other cells not allowed in that bound Group bounds means without any location and coordination's group bounds are two types soft and hard group bounds.

  Netlist quality checks Below are certain checks that, should be fulfilled post-synthesis to ensure netlist qualifications before it is delivered for physical implementation. 1. No Clocks: In this check, we ensure that all the required clocks reach the sync points. Some major reasons for getting no clock violation in design are mentioned below: Clock definition missing: This is observed when clock creation is missing in the clock constraint file. RTL connectivity issue/Tie off: This type of no clock is observed when there is missing connectivity in between modules in the RTL or having direct tie-offs in the RTL. Impact:  Ideally, all the registers in the design should be clocked. If no clock issue is left in the design, then it will report unconstraint endpoints and can cause optimization issues on such paths. Solution:  To resolve the above-mentioned no clocks violation, we need to get the corrected RTL (from the designer) and clock constraints files with all the required clock defin

  In a   VLSI design , floorplan is the crucial stage in which chip area, size and shape of the chip can be determined. Floorplan is iterative process. When designer is done with the floorplan, the next step is to run placement and optimization, after completion of placement and optimization designer would analyse the congestion map, cell density and timing reports, before moving to next stage i.e. Clock Tree Synthesis. This article discusses about the various approaches to reduce congestion and timing violation by modifying floorplan at block level. The design complexity is increasing as the number of transistors on a chip is increasing. So, in the   VLSI design flow , Physical design plays a very important role. Floorplanning is the starting step in the physical design flow. The main concern of floorplanning is to find the appropriate location of the module on the layout surface on the basis of interconnectivity. While determining the locations, one important check involved is that t

  Congestion in VLSI (Very large-scale Integration) design refers to the circumstance when the number of routing tracks is less than the required routing tracks. These routing resources are used to connect all the required wires between the different components of the design. PnR tool highlights congested areas as red hotspots, as depicted in figure 1. As the complexity of the design increases, congestion has become a major issue in chip design that requires careful consideration and optimization to ensure that the design meets the required timing, power, and area constraints. Fig-1 Congestion report: GRC: The term GRC is an abbreviation of Global Routing Cells. During the initial placement, the core area gets divided into equally sized small squares called GRC. Overflow total: The summation of the total number of overflow routes for all GRCs. In the above report, it is 1,384,599.Overflow Max: “Both Dirs” means combined results for both horizontal and vertical routing directions. Max i