1.
What is signal integrity? How it affects
Timing?
2.
What is IR drop? How to avoid .how it affects
timing?
3.
What is EM and it effects?
4.
What is floor plan and power plan?
5.
What are types of routing?
6.
What is a grid .why we need and different
types of grids?
7.
What is core and how u will decide w/h ratio
for core?
8.
What is effective utilization and chip utilization?
9.
What is latency? Give the types?
10.
What is LEF?
11.
What is DEF?
12.
What are the steps involved in designing an
optimal pad ring?
13.
What are the steps that you have done in the
design flow?
14.
What are the issues in floor plan?
15.
How can you estimate area of block?
16.
How much aspect ratio should be kept (or have
you kept) and what is the utilization?
17.
How to calculate core ring and stripe widths?
18.
What if hot spot found in some area of block?
How you tackle this?
19.
After adding stripes also if you have hot spot
what to do?
20.
What is threshold voltage? How it affect
timing?
21.
What is content of lib, lef, sdc?
22.
What is meant my 9 track, 12 track standard
cells?
23.
What is scan chain? What if scan chain not
detached and reordered? Is it compulsory?
24.
What is setup and hold? Why there are ? What
if setup and hold violates?
25.
In a circuit, for reg to reg path ...Tclktoq
is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum
operating frequency?
26.
How R and C values are affecting time?
27.
How ohm (R), fared (C) is related to second
(T)?
28.
What is transition? What if transition time is
more?
29.
What is difference between normal buffer and
clock buffer?
30.
What is antenna effect? How it is avoided?
31.
What is ESD?
32.
What is cross talk? How can you avoid?
33.
How double spacing will avoid cross talk?
34.
What is difference between HFN synthesis and
CTS?
35.
What is hold problem? How can you avoid it?
36.
For an iteration we have 0.5ns of insertion
delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew
for the same circuit then which one you will select? Why?
37.
What is partial floor plan?
38.
What parameters (or aspects) differentiate
Chip Design & Block level design??
39.
How do you place macros in a full chip design?
40.
Differentiate between a Hierarchical Design
and flat design?
41.
Which is more complicated when u have a 48 MHz
and 500 MHz clock design?
42.
Name few tools which you used for physical
verification?
43.
What are the input files will you give for
primetime correlation?
44.
What are the algorithms used while routing?
Will it optimize wire length?
45.
How will you decide the Pin location in block
level design?
46.
If the routing congestion exists between two
macros, then what will you do?
47.
How will you place the macros?
48.
How will you decide the die size?
49.
If lengthy metal layer is connected to
diffusion and poly, then which one will affect by antenna problem?
50.
If the full chip design is routed by 7 layer
metal, why macros are designed using 5LM instead of using 7LM?
51.
In your project what is die size, number of
metal layers, technology, foundry, number of clocks?
52.
How many macros in your design?
53.
What is each macro size and no. of standard
cell count?
54.
How did u handle the Clock in your design?
55.
What are the Input needs for your design?
56.
What is SDC constraint file contains?
57.
How did you do power planning?
58.
How to find total chip power?
59.
How to calculate core ring width, macro ring
width and strap or trunk width?
60.
How to find number of power pad and IO power
pads?
61.
What are the problems faced related to timing?
62.
How did u resolve the setup and hold problem?
63.
If in your design 10000 and more numbers of
problems come, then what you will do?
64.
In which layer do you prefer for clock routing
and why?
65.
If in your design has reset pin, then it’ll
affect input pin or output pin or both?
66.
During power analysis, if you are facing IR
drop problem, then how did u avoid?
67.
Define antenna problem and how did u resolve
these problem?
68.
How delays vary with different PVT conditions?
Show the graph.
69.
Explain the flow of physical design and inputs
and outputs for each step in flow.
70.
What is cell delay and net delay?
71.
What are delay models and what is the
difference between them?
72.
What is wire load model?
73.
What does SDC constraints has?
74.
Why higher metal layers are preferred for Vdd
and Vss?
75.
What is logic optimization and give some
methods of logic optimization.
76.
What is the significance of negative slack?
77.
How the width of metal and number of straps
calculated for power and ground?
78.
What is negative slack ? How it affects
timing?
79.
What is track assignment?
80.
What is grided and gridless routing?
81.
What is a macro and standard cell?
82.
What is congestion?
83.
Whether congestion is related to placement or
routing?
84.
What are clock trees?
85.
What are clock tree types?
86.
Which layer is used for clock routing and why?
87.
What is cloning and buffering?
88.
What are placement blockages?
89.
How slow and fast transition at inputs effect
timing for gates?
90.
What is antenna effect?
91.
What are DFM issues?
92.
What is .lib, LEF, DEF, .tf?
93.
What is the difference between synthesis and
simulation?
94.
What is metal density, metal slotting rule?
95.
What is OPC, PSM?
96.
Why clock is not synthesized in DC?
97.
What are high-Vt and low-Vt cells?
98.
What corner cells contains?
99.
What is the difference between core filler
cells and metal fillers?
100.
How to decide number of pads in chip level
design?
101.
What is tie-high and tie-low cells and where
it is used What is signal integrity? How
it affects Timing?
102.
What is IR drop? How to avoid .how it affects
timing?
103.
What is EM and it effects?
104.
What is floor plan and power plan?
105.
What are types of routing?
106.
What is a grid .why we need and different
types of grids?
107.
What is core and how u will decide w/h ratio
for core?
108.
What is effective utilization and chip
utilization?
109.
What is latency? Give the types?
110.
What is LEF?
111.
What is DEF?
112.
What are the steps involved in designing an
optimal pad ring?
113.
What are the steps that you have done in the
design flow?
114.
What are the issues in floor plan?
115.
How can you estimate area of block?
116.
How much aspect ratio should be kept (or have
you kept) and what is the utilization?
117.
How to calculate core ring and stripe widths?
118.
What if hot spot found in some area of block?
How you tackle this?
119.
After adding stripes also if you have hot spot
what to do?
120.
What is threshold voltage? How it affect
timing?
121.
What is content of lib, lef, sdc?
122.
What is meant my 9 track, 12 track standard
cells?
123.
What is scan chain? What if scan chain not
detached and reordered? Is it compulsory?
124.
What is setup and hold? Why there are ? What
if setup and hold violates?
125.
In a circuit, for reg to reg path ...Tclktoq
is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum
operating frequency?
126.
How R and C values are affecting time?
127.
How ohm (R), fared (C) is related to second
(T)?
128.
What is transition? What if transition time is
more?
129.
What is difference between normal buffer and
clock buffer?
130.
What is antenna effect? How it is avoided?
131.
What is ESD?
132.
What is cross talk? How can you avoid?
133.
How double spacing will avoid cross talk?
134.
What is difference between HFN synthesis and
CTS?
135.
What is hold problem? How can you avoid it?
136.
For an iteration we have 0.5ns of insertion
delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew
for the same circuit then which one you will select? Why?
137.
What is partial floor plan?
138.
What parameters (or aspects) differentiate
Chip Design & Block level design??
139.
How do you place macros in a full chip design?
140.
Differentiate between a Hierarchical Design
and flat design?
141.
Which is more complicated when u have a 48 MHz
and 500 MHz clock design?
142.
Name few tools which you used for physical
verification?
143.
What are the input files will you give for
primetime correlation?
144.
What are the algorithms used while routing?
Will it optimize wire length?
145.
How will you decide the Pin location in block
level design?
146.
If the routing congestion exists between two
macros, then what will you do?
147.
How will you place the macros?
148.
How will you decide the die size?
149.
If lengthy metal layer is connected to
diffusion and poly, then which one will affect by antenna problem?
150.
If the full chip design is routed by 7 layer
metal, why macros are designed using 5LM instead of using 7LM?
151.
In your project what is die size, number of
metal layers, technology, foundry, number of clocks?
152.
How many macros in your design?
153.
What is each macro size and no. of standard
cell count?
154.
How did u handle the Clock in your design?
155.
What are the Input needs for your design?
156.
What is SDC constraint file contains?
157.
How did you do power planning?
158.
How to find total chip power?
159.
How to calculate core ring width, macro ring
width and strap or trunk width?
160.
How to find number of power pad and IO power
pads?
161.
What are the problems faced related to timing?
162.
How did u resolve the setup and hold problem?
163.
If in your design 10000 and more numbers of
problems come, then what you will do?
164.
In which layer do you prefer for clock routing
and why?
165.
If in your design has reset pin, then it’ll
affect input pin or output pin or both?
166.
During power analysis, if you are facing IR
drop problem, then how did u avoid?
167.
Define antenna problem and how did u resolve
these problem?
168.
How delays vary with different PVT conditions?
Show the graph.
169.
Explain the flow of physical design and inputs
and outputs for each step in flow.
170.
What is cell delay and net delay?
171.
What are delay models and what is the
difference between them?
172.
What is wire load model?
173.
What does SDC constraints has?
174.
Why higher metal layers are preferred for Vdd
and Vss?
175.
What is logic optimization and give some
methods of logic optimization.
176.
What is the significance of negative slack?
177.
How the width of metal and number of straps
calculated for power and ground?
178.
What is negative slack ? How it affects
timing?
179.
What is track assignment?
180.
What is grided and gridless routing?
181.
What is a macro and standard cell?
182.
What is congestion?
183.
Whether congestion is related to placement or
routing?
184.
What are clock trees?
185.
What are clock tree types?
186.
Which layer is used for clock routing and why?
187.
What is cloning and buffering?
188.
What are placement blockages?
189.
How slow and fast transition at inputs effect
timing for gates?
190.
What is antenna effect?
191.
What are DFM issues?
192.
What is .lib, LEF, DEF, .tf?
193.
What is the difference between synthesis and
simulation?
194.
What is metal density, metal slotting rule?
195.
What is OPC, PSM?
196.
Why clock is not synthesized in DC?
197.
What are high-Vt and low-Vt cells?
198.
What corner cells contains?
199.
What is the difference between core filler
cells and metal fillers?
200.
How to decide number of pads in chip level
design?
201.
What is tie-high and tie-low cells and where
it is used
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