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Temperature inversion

 What is Temp Inversion?

As the temperature increases, the delay of the cell can

  • Decrease due to decrease in threshold voltage (Vt).
  • Increase due to decrease in the mobility.

Delay of a cell may decrease or increase depending on the dominant effect of mobility and threshold voltage (Vt), that is what defines the resulting thermal trend related to temperature inversion effects.

If Gate overdrive voltage (Vdd - Vt) is large then the decrease in threshold voltage due to temperature variation is negligible. But the mobility effect dominates, with the result that the delay of the gate increases with temperature increases.

But, if Gate overdrive voltage (Vdd - Vt) has reduced such that the decrease in threshold voltage effect dominates and delay decreases with the increases in temperature.

So, at 65nm and below, the threshold voltage (Vt) has not been reduced much but the supply voltages has reduced considerably to cater low leakage power concerns. The result is that the gate overdrive voltage (Vdd - Vt) has reduced and thus more prominent temperature inversion effects are observed.

Fig 1: Temperature inversion at different voltages and for different Vt flavors.

From the above graph, it is clear that Temp. Inversion effect tends to come into picture at lower voltages with more prominent effect on Higher Vt cells. Temp. Inversion effect will be more in lower technology nodes.

Fig 2: Temperature Inversion effect @different input transitions for HVT cell

Better Transition in design would :-

  • Suppress the effect of temperature inversion.
  • Help to meet higher frequency targets.
  • Reduce the internal power.

But better transition would require high drive strength or more Low Vt cells or more redundant buffers in the design which leads to: -

  • More leakage power.
  • More switching power.

This increase in power is not acceptable!!!

Traditional Approach: For better power optimization, design is optimized first using High Vt cells and later Low Vt cells are exposed for incremental timing optimization in timing critical path only. Since HVT cell (High Vt, which is most susceptible to variation) is driving LVT logic, it will lead to more variation in design as well as more power dissipation.

Proposed Approach using Intelligent Vt structuring: Structuring is such that wherever High Vt cell is driving Low Vt cell, replace that occurrence with Low Vt cell driving the High Vt cell without degrading:-

  • Slew values.
  • Timing.
  • Leakage Power.

Fig.3: Traditional vs Proposed Approach

Below are the analysis results on the cell level implementation of the above described approaches.

Fig.4: Cell level results comparison for Traditional vs Proposed Approach

Design Implementation Algorithm:


Conclusion: -

As discussed above, it has always been a tedious and iterative task in complex designs to close the timing as it is not possible to live without multi-Vt(threshold voltage) and multi-voltage domains anymore due to more pronounced leakage concerns, higher frequency requirements, low power solutions at lower technology nodes. Using the LVT (Low-threshold devices, Low Vt) devices in the early paths which eventually give the benefits both in terms of the delay and power consumption.

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