Skip to main content

Temperature inversion

 What is Temp Inversion?

As the temperature increases, the delay of the cell can

  • Decrease due to decrease in threshold voltage (Vt).
  • Increase due to decrease in the mobility.

The dominating impacts of mobility and threshold voltage (Vt) determine the ensuing thermal trend associated with temperature inversion effects, which can cause a cell's delay to either increase or decrease.

The threshold voltage drop brought on by temperature change is minimal if the gate overdrive voltage (Vdd - Vt) is high. However, the mobility effect predominates, which causes the gate's delay to increase as the temperature rises.

But, if Gate overdrive voltage (Vdd - Vt) has reduced such that the decrease in threshold voltage effect dominates and delay decreases with the increases in temperature.

 below nodes, the threshold voltage (Vt) has not been reduced much but the supply voltages has reduced considerably to cater low leakage power concerns. The result is that the gate overdrive voltage (Vdd - Vt) has reduced and thus more prominent temperature inversion effects are observed.

Fig 1: Temperature inversion at different voltages and for different Vt flavors.

From the above graph, it is clear that Temp. Inversion effect tends to come into picture at lower voltages with more prominent effect on Higher Vt cells. Temp. Inversion effect will be more in lower technology nodes.

Fig 2: Temperature Inversion effect @different input transitions for HVT cell

Traditional Approach: High Vt cells are used to refine the design initially for greater power optimization, and then Low Vt cells are revealed for incremental timing optimization in the timing critical path alone. More design variation and power consumption will result from the HVT cell (High Vt, which is most prone to variation) driving the LVT logic.

Proposed Approach using Intelligent Vt structuring: Structuring is such that wherever High Vt cell is driving Low Vt cell, replace that occurrence with Low Vt cell driving the High Vt cell without degrading:-

  • Slew values.
  • Timing.
  • Leakage Power.

Fig.3: Traditional vs Proposed Approach

Below are the analysis results on the cell level implementation of the above described approaches.

Fig.4: Cell level results comparison for Traditional vs Proposed Approach

Design Implementation Algorithm:


Better Transition in design would :-

  • Suppress the effect of temperature inversion.
  • Help to meet higher frequency targets.
  • Reduce the internal power.

But better transition would require high drive strength or more Low Vt cells or more redundant buffers in the design which leads to: -

  • More leakage power.
  • More switching power.

This increase in power is not acceptable!!!

Comments

Popular posts from this blog

unlock surprise too see commands

                                  SynopsysTool Commands                                       How to add ndms in ref_libs Open block.tcl file Report_ref_libs information dump in a new tcl file Now go to icc2shell set_ref_libs -add missed ndm file---> from block.tcl file set_ref_libs -rebind link_block -force report_ref_libs save_block save_lib How to resolve upf error ? commit_upf save_block save_lib How to move ESD cell with origin coordinates ? move_objects [get_selection ] -to {7486.0965 3288.0000} How to select all the cells which have net name VDD_1V2_IO ?  change_selection [get_cells -of_objects [get_net VDD_1V2_IO]] Cmd for to check shorts  check_lvs -max_error 0 -checks short ----->for to check shorts How to add buffers add_buffer -lib_cell ec0cbf000an1n20x5 -new_cell_names 01122...

QUESTION&ANSWERS

  Q 1: What are the goals of Synthesis ? There are Mainly three goals of synthesis without changing the functionality Reduce the area (chip cost reduce) Increase performance Reduce the power Q 2: What are the Tech dependent inputs in PNR There are three main tech depended inputs Physical libraries    -->format is .lef     --->given by vendors Technology file       -->format is .tf       --->given by fabrication peoples TLU+ file                   -->format is .TLUP-->given by fabrication people Q 3: What are the Design dependent inputs in PNR There are six main design depended inputs Logical libraries      --> format is .lib    --->given by Vendors Netlist          ...

Multiple Voltage Design

MODERN TECHNIQUES                                                      Modern IC designs are heavily influenced by the need to minimize power consumption, particularly in the consumer electronics market. The devices' warmth, battery life, and the time it takes to switch on and off the functions of handheld devices are currently being reformed. Therefore, it becomes crucial to implement best practices in chip design to help reduce power consumption in SoCs (System on Chip). The power management of SoCs and RTL designs has a significant impact on the silicon's performance. Power-aware designs are used by industry to achieve power statistics. This blog focuses on multi-voltage design terms that can be used to assess the power performance of silicon in HDL coding. These facilitate the understanding of design parameters while implementing power-consciou...