BackendVLSI

                                  SynopsysTool Commands                                       How to add ndms in ref_libs Open block.tcl file Report_ref_libs information dump in a new tcl file Now go to icc2shell set_ref_libs -add missed ndm file---> from block.tcl file set_ref_libs -rebind link_block -force report_ref_libs save_block save_lib How to resolve upf error ? commit_upf save_block save_lib How to move ESD cell with origin coordinates ? move_objects [get_selection ] -to {7486.0965 3288.0000} How to select all the cells which have net name VDD_1V2_IO ?  change_selection [get_cells -of_objects [get_net VDD_1V2_IO]] Cmd for to check shorts  check_lvs -max_error 0 -checks short ----->for to check shorts How to add buffers add_buffer -lib_cell ec0cbf000an1n20x5 -new_cell_names 01122...

 Outlined the tasks involved in the floorplanning phase of the chip design process. Here's a detailed breakdown of the steps. 1]Invoke the Tool 2]Open the Library and Block Created 3]Perform Sanity Checks 4]Create a Floorplan Define the core utilization, aspect ratio (width vs. height), chip shape, and space between the core and the die area. 5]Placing the I/O Ports 6]Placing Macros into the Core Area: 7]Set Keepout Margin and Fix the Macros 8]Add End Cap Cells 9]Add Tap Cells  10] Check Legality POWER PLANNING :  The power planning stage is a critical step in chip design, laying the groundwork for efficient and reliable power delivery throughout the chip. It's like building a robust power grid for your miniature city of transistors!  Goals of Power Planning: 1]Provide Efficient Power Supply to each component in the design 2]Power grid should meet the set IR drop targets. 3]Power grid should meet all EM targets. 4]Power grid should be optimal in terms of resource usa...

  What is Temp Inversion? As the temperature increases, the delay of the cell can Decrease due to decrease in threshold voltage (Vt). Increase due to decrease in the mobility. The dominating impacts of mobility and threshold voltage (Vt) determine the ensuing thermal trend associated with temperature inversion effects, which can cause a cell's delay to either increase or decrease. The threshold voltage drop brought on by temperature change is minimal if the gate overdrive voltage (Vdd - Vt) is high. However, the mobility effect predominates, which causes the gate's delay to increase as the temperature rises. But, if Gate overdrive voltage (Vdd - Vt) has reduced such that the decrease in threshold voltage effect dominates and delay decreases with the increases in temperature.  below nodes, the threshold voltage (Vt) has not been reduced much but the supply voltages has reduced considerably to cater low leakage power concerns. The result is that the gate overdrive voltage (Vdd -...

MODERN TECHNIQUES                                                      Modern IC designs are heavily influenced by the need to minimize power consumption, particularly in the consumer electronics market. The devices' warmth, battery life, and the time it takes to switch on and off the functions of handheld devices are currently being reformed. Therefore, it becomes crucial to implement best practices in chip design to help reduce power consumption in SoCs (System on Chip). The power management of SoCs and RTL designs has a significant impact on the silicon's performance. Power-aware designs are used by industry to achieve power statistics. This blog focuses on multi-voltage design terms that can be used to assess the power performance of silicon in HDL coding. These facilitate the understanding of design parameters while implementing power-consciou...

  What are the types of bounds ? There are two types of bounds move bound and group bound & Move bounds means with definite coordinate if we created bound that's we called move bounds this are three types Soft move bound: In optimization some cells are go out from the bound to meet timing QOR other logic cell comes and site in that bound Hard move bound: The cells should not move out and other cells are allowed in that bound Exclusive move bound : The cells not move out and other cells not allowed in that bound Group bounds means without any location and coordination's group bounds are two types soft and hard group bounds.

  Netlist quality checks Below are certain checks that, should be fulfilled post-synthesis to ensure netlist qualifications before it is delivered for physical implementation. 1. No Clocks: In this check, we ensure that all the required clocks reach the sync points. Some major reasons for getting no clock violation in design are mentioned below: Clock definition missing: This is observed when clock creation is missing in the clock constraint file. RTL connectivity issue/Tie off: This type of no clock is observed when there is missing connectivity in between modules in the RTL or having direct tie-offs in the RTL. Impact:  Ideally, all the registers in the design should be clocked. If no clock issue is left in the design, then it will report unconstraint endpoints and can cause optimization issues on such paths. Solution:  To resolve the above-mentioned no clocks violation, we need to get the corrected RTL (from the designer) and clock constraints files with all the requir...